📄 des3des.c
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/*******************************************************************************
TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
Property of Texas Instruments
For Unrestricted Internal Use Only
Unauthorized reproduction and/or distribution is strictly prohibited.
This product is protected under copyright law and trade secret law
as an unpublished work.
Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved.
Filename : des3des.c
============================== TEST DESCRIPTION ===============================
*/
#include "des3des.h"
#include "global_types.h"
#include "des3des.h"
#include "errorcodes.h"
#include "testaccess.h"
#define BUFFER_SIZE 8
#define EXCESS 8
#define FRAMES_TO_TX 4 // 4 frames of 8 bytes
#define FRAMES_TO_RX 4
#define TOTAL_TXRX_SIZE (FRAMES_TO_TX * BUFFER_SIZE)
/* Externs */
extern int DmaCount;
extern UWORD32 * const ram_Resdata;
extern UWORD32 * const ram_Srcdata;
extern UWORD32 aKey1L;
extern UWORD32 aKey1H;
//---------------------------------------------------------------------
// NAME : DES3DES_TestResetValue
//
// DESCRIPTION : Test the reset values of DES3DES registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void DES3DES_Test_ResetValue(void)
{
BEGIN_RESET_MODULE();
BEGIN_RESET_TEST(DES3DES_DES_KEY3_L,32);
TEST_FIELD_RESET(DES3DES_DES_KEY3_L,DES_KEY3_L,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_KEY3_H,32);
TEST_FIELD_RESET(DES3DES_DES_KEY3_H,DES_KEY3_H,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_KEY2_L,32);
TEST_FIELD_RESET(DES3DES_DES_KEY2_L,DES_KEY2_L,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_KEY2_H,32);
TEST_FIELD_RESET(DES3DES_DES_KEY2_H,DES_KEY2_H,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_KEY1_L,32);
TEST_FIELD_RESET(DES3DES_DES_KEY1_L,DES_KEY1_L,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_KEY1_H,32);
TEST_FIELD_RESET(DES3DES_DES_KEY1_H,DES_KEY1_H,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_IV_L,32);
TEST_FIELD_RESET(DES3DES_DES_IV_L,DES_IV_L,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_IV_H,32);
TEST_FIELD_RESET(DES3DES_DES_IV_H,DES_IV_H,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_CTRL,32);
// TEST_FIELD_RESET(DES3DES_DES_CTRL,RESERVED,32);
TEST_FIELD_RESET(DES3DES_DES_CTRL,CBC,32);
TEST_FIELD_RESET(DES3DES_DES_CTRL,TDES,32);
TEST_FIELD_RESET(DES3DES_DES_CTRL,DIRECTION,32);
TEST_FIELD_RESET(DES3DES_DES_CTRL,INPUT_READY,32);
TEST_FIELD_RESET(DES3DES_DES_CTRL,OUTPUT_READY,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_DATA_L,32);
TEST_FIELD_RESET(DES3DES_DES_DATA_L,DES_DATA_L,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_DATA_H,32);
TEST_FIELD_RESET(DES3DES_DES_DATA_H,DES_DATA_H,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_REV,32);
// TEST_FIELD_RESET(DES3DES_DES_REV,RESERVED,32);
TEST_FIELD_RESET(DES3DES_DES_REV,REV_NB,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_MASK,32);
// TEST_FIELD_RESET(DES3DES_DES_MASK,RESERVED,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,START,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,DIRECT_BUS_EN,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,DMA_REQ_OUT_EN,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,DMA_REQ_IN_EN,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,SOFTRESET,32);
TEST_FIELD_RESET(DES3DES_DES_MASK,AUTOIDLE,32);
END_RESET_TEST();
BEGIN_RESET_TEST(DES3DES_DES_SYSSTATUS,32);
// TEST_FIELD_RESET(DES3DES_DES_SYSSTATUS,RESERVED,32);
//DES3DES_DES_SYSSTATUS,RESETDONE of DES3DES_DES_SYSSTATUS has unknown reset value;
END_RESET_TEST();
END_RESET_MODULE();
}
//---------------------------------------------------------------------
// NAME : DES3DES_TestRegistersAccess
//
// DESCRIPTION : Test the access to DES3DES registers
//
// PARAMETERS : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void DES3DES_TestRegistersAccess(void)
{
BEGIN_ACCESS_MODULE();
// All following registers which are commented returns 0 when they are read
/* BEGIN_RW_TEST(DES3DES_DES_KEY3_L,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY3_L,DES_KEY3_L,32);
RW_WRITE(DES3DES_DES_KEY3_L);
RW_TEST_READ(DES3DES_DES_KEY3_L,DES_KEY3_L,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY3_L);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_KEY3_H,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY3_H,DES_KEY3_H,32);
RW_WRITE(DES3DES_DES_KEY3_H);
RW_TEST_READ(DES3DES_DES_KEY3_H,DES_KEY3_H,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY3_H);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_KEY2_L,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY2_L,DES_KEY2_L,32);
RW_WRITE(DES3DES_DES_KEY2_L);
RW_TEST_READ(DES3DES_DES_KEY2_L,DES_KEY2_L,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY2_L);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_KEY2_H,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY2_H,DES_KEY2_H,32);
RW_WRITE(DES3DES_DES_KEY2_H);
RW_TEST_READ(DES3DES_DES_KEY2_H,DES_KEY2_H,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY2_H);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_KEY1_L,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY1_L,DES_KEY1_L,32);
RW_WRITE(DES3DES_DES_KEY1_L);
RW_TEST_READ(DES3DES_DES_KEY1_L,DES_KEY1_L,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY1_L);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_KEY1_H,32);
RW_PREPARE_WRITE(DES3DES_DES_KEY1_H,DES_KEY1_H,32);
RW_WRITE(DES3DES_DES_KEY1_H);
RW_TEST_READ(DES3DES_DES_KEY1_H,DES_KEY1_H,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_KEY1_H);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_IV_L,32);
RW_PREPARE_WRITE(DES3DES_DES_IV_L,DES_IV_L,32);
RW_WRITE(DES3DES_DES_IV_L);
RW_TEST_READ(DES3DES_DES_IV_L,DES_IV_L,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_IV_L);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_IV_H,32);
RW_PREPARE_WRITE(DES3DES_DES_IV_H,DES_IV_H,32);
RW_WRITE(DES3DES_DES_IV_H);
RW_TEST_READ(DES3DES_DES_IV_H,DES_IV_H,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_IV_H);
END_RW_TEST();*/
BEGIN_RW_TEST(DES3DES_DES_CTRL,32);
// RW_PREPARE_WRITE(DES3DES_DES_CTRL,RESERVED,32);
RW_PREPARE_WRITE(DES3DES_DES_CTRL,CBC,32);
RW_PREPARE_WRITE(DES3DES_DES_CTRL,TDES,32);
RW_PREPARE_WRITE(DES3DES_DES_CTRL,DIRECTION,32);
//DES3DES_DES_CTRL,INPUT_READY is Read Only
//DES3DES_DES_CTRL,OUTPUT_READY is Read Only
RW_WRITE(DES3DES_DES_CTRL);
// RW_TEST_READ(DES3DES_DES_CTRL,RESERVED,32);
RW_TEST_READ(DES3DES_DES_CTRL,CBC,32);
RW_TEST_READ(DES3DES_DES_CTRL,TDES,32);
RW_TEST_READ(DES3DES_DES_CTRL,DIRECTION,32);
//DES3DES_DES_CTRL,INPUT_READY is Read Only
//DES3DES_DES_CTRL,OUTPUT_READY is Read Only
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_CTRL);
END_RW_TEST();
//Read values are encrypted values and written values are values
// to be encrypted, so it's in fact 2 different registers
/* BEGIN_RW_TEST(DES3DES_DES_DATA_L,32);
RW_PREPARE_WRITE(DES3DES_DES_DATA_L,DES_DATA_L,32);
RW_WRITE(DES3DES_DES_DATA_L);
RW_TEST_READ(DES3DES_DES_DATA_L,DES_DATA_L,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_DATA_L);
END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_DATA_H,32);
RW_PREPARE_WRITE(DES3DES_DES_DATA_H,DES_DATA_H,32);
RW_WRITE(DES3DES_DES_DATA_H);
RW_TEST_READ(DES3DES_DES_DATA_H,DES_DATA_H,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_DATA_H);
END_RW_TEST();*/
// BEGIN_RW_TEST(DES3DES_DES_REV,32);
// RW_PREPARE_WRITE(DES3DES_DES_REV,RESERVED,32);
//DES3DES_DES_REV,REV_NB is Read Only
// RW_WRITE(DES3DES_DES_REV);
// RW_TEST_READ(DES3DES_DES_REV,RESERVED,32);
//DES3DES_DES_REV,REV_NB is Read Only
// RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_REV);
// END_RW_TEST();
BEGIN_RW_TEST(DES3DES_DES_MASK,32);
// RW_PREPARE_WRITE(DES3DES_DES_MASK,RESERVED,32);
RW_PREPARE_WRITE(DES3DES_DES_MASK,START,32);
RW_PREPARE_WRITE(DES3DES_DES_MASK,DIRECT_BUS_EN,32);
RW_PREPARE_WRITE(DES3DES_DES_MASK,DMA_REQ_OUT_EN,32);
RW_PREPARE_WRITE(DES3DES_DES_MASK,DMA_REQ_IN_EN,32);
// RW_PREPARE_WRITE(DES3DES_DES_MASK,SOFTRESET,32); Soft reset must not be written
RW_PREPARE_WRITE(DES3DES_DES_MASK,AUTOIDLE,32);
RW_WRITE(DES3DES_DES_MASK);
// RW_TEST_READ(DES3DES_DES_MASK,RESERVED,32);
RW_TEST_READ(DES3DES_DES_MASK,START,32);
RW_TEST_READ(DES3DES_DES_MASK,DIRECT_BUS_EN,32);
RW_TEST_READ(DES3DES_DES_MASK,DMA_REQ_OUT_EN,32);
RW_TEST_READ(DES3DES_DES_MASK,DMA_REQ_IN_EN,32);
// RW_TEST_READ(DES3DES_DES_MASK,SOFTRESET,32); Soft reset must not be written
RW_TEST_READ(DES3DES_DES_MASK,AUTOIDLE,32);
RW_WRITE_PREVIOUS_VALUE(DES3DES_DES_MASK);
END_RW_TEST();
END_ACCESS_MODULE();
}
int DES_SetCtrlReg(const BIT desMode, const BIT cbcMode, const BIT direction) {
register UWORD32 tmp, ptr32 = 0;
tmp = DES3DES_DES_CTRL ;
if (desMode) { // des mode -> 0, 3desmode -> 0x8
ptr32 |= 0x0008;
}
if (cbcMode) {
ptr32 |= 0x0010;
}
if (direction) { // encryption -> 0x4, Decryption -> 0x0
ptr32 |= 0x0004;
}
DES3DES_DES_CTRL |= ptr32;
ptr32 = DES3DES_DES_CTRL;
return 1;
}
int DES_SetMaskReg(const BIT directBusConf, const BIT dmaConf, const BIT clkConf) {
register UWORD32 tmp, ptr32 = 0;
UWORD32 ret_test;
tmp = DES3DES_DES_MASK;
if (directBusConf) {
ptr32 |= 0x10;
}
else {}
if (dmaConf) // full dma, Dma_req_in and dma_Req_Out
ptr32 |= 0xc;
else {}
if (clkConf) {
ptr32 |= 0x1;
}
else {}
DES3DES_DES_MASK = ptr32;
ptr32 = DES3DES_DES_MASK;
return 1;
}
int DES_LoadKey(struct Key_struct *aBunch) {
DES3DES_DES_KEY1_H = aBunch->Key1H;
DES3DES_DES_KEY1_L = aBunch->Key1L;
if (aBunch->desmode == 1) {
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