wcdma_cks.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}

void WCDMA_CksSetupAllModulesVctcxoOnly(void)
{
//
// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000222;
CKS_CLK_SEL_REG4 = 0x00000AAA;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000001;
CKS_MDM_PDIV_SEL_REG = 0x00000101;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000000;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}


// Setup CKS module (clocks and resets) for generic setup
void WCDMA_CksSetupAllModules(void)
{
//
// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000602;
CKS_CLK_SEL_REG4 = 0x00000E8A;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to byPass the DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000001;
CKS_MDM_PDIV_SEL_REG = 0x00000101;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}






// Setup CKS module (clocks and resets) for RX Chain test
void WCDMA_CksSetupRXChainTest(void)
{
//
// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000602;
CKS_CLK_SEL_REG4 = 0x00000E8A;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem Input Clock (32x) to VCTCXO (bypass APLL and DPLL)
CKS_MDM_PDIV_SEL_REG = 0x00000001;
CKS_MDM_PDIV_SEL_REG = 0x00000101;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks for RX chain modules
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
// turn on DEC, SC, CTR
CKS_CLK_EN_REG2 = 0xFFFF0E09;
// turn on CCP, MRC, FSB
CKS_CLK_EN_REG3 = 0xFFFFFFF1;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}




// Setup CKS module (clocks and resets) for RCI test
void WCDMA_CksSetupRCITest(void)
{
//
// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000660;
CKS_CLK_SEL_REG4 = 0x00000EE8;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}


// Setup CKS module (clocks and resets) for RCI test. Engages the DPLL and APLL models
void WCDMA_CksSetupRCITestEngageEnablePll(void)
{
//
int cntr_apll =0;
int cntr_dpll =0;
// Select Clocks
//Enable APLL and then enable DPLL.
CKS_WCDMA_APLL_CNTL_REG = 0x00000002;
//Await lock 100us, hence the counter.
while (cntr_apll <300){
cntr_apll++;
}
CKS_WCDMA_DPLL_CNTL_REG = 0x00012410;
CKS_WCDMA_DPLL_CNTL_REG = 0x80012410;
//Await lock 300us, hence the counter.
while (cntr_dpll <1000) {
cntr_dpll++;
}



// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000660;
CKS_CLK_SEL_REG4 = 0x00000EE8;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}