wcdma_cks.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

RES_Set((CKS_PMT_SEL_REG & CKS_PMT_SEL_REG_WR_MASK) >> 16);
RES_Set((CKS_PMT_SEL_REG & CKS_PMT_SEL_REG_WR_MASK) & 0xFFFF);
RES_Set((~CKS_PMT_SEL_REG_RES_VAL & CKS_PMT_SEL_REG_WR_MASK) >> 16);
RES_Set((~CKS_PMT_SEL_REG_RES_VAL & CKS_PMT_SEL_REG_WR_MASK) & 0xFFFF);
RES_Set(END_ARRAY_DATA);
}

if (global_test == 1) {
RES_Set(TEST_OK);
}

// Put the registers back to its reset values
CKS_CLK_EN_REG1 =(CKS_CLK_EN_REG1_RES_VAL & CKS_CLK_EN_REG1_WR_MASK);
CKS_CLK_EN_REG2 =(CKS_CLK_EN_REG2_RES_VAL & CKS_CLK_EN_REG2_WR_MASK);
CKS_CLK_EN_REG3 =(CKS_CLK_EN_REG3_RES_VAL & CKS_CLK_EN_REG3_WR_MASK);
CKS_CLK_EN_REG4 =(CKS_CLK_EN_REG4_RES_VAL & CKS_CLK_EN_REG4_WR_MASK);
CKS_SLP_EN_REG1 =(CKS_SLP_EN_REG1_RES_VAL & CKS_SLP_EN_REG1_WR_MASK);
CKS_SLP_EN_REG2 =(CKS_SLP_EN_REG2_RES_VAL & CKS_SLP_EN_REG2_WR_MASK);
CKS_SLP_EN_REG3 =(CKS_SLP_EN_REG3_RES_VAL & CKS_SLP_EN_REG3_WR_MASK);
CKS_SLP_EN_REG4 =(CKS_SLP_EN_REG4_RES_VAL & CKS_SLP_EN_REG4_WR_MASK);
CKS_RST_EN_REG1 =(CKS_RST_EN_REG1_RES_VAL & CKS_RST_EN_REG1_WR_MASK);
CKS_RST_EN_REG2 =(CKS_RST_EN_REG2_RES_VAL & CKS_RST_EN_REG2_WR_MASK);
CKS_RST_EN_REG3 =(CKS_RST_EN_REG3_RES_VAL & CKS_RST_EN_REG3_WR_MASK);
CKS_RST_EN_REG4 =(CKS_RST_EN_REG4_RES_VAL & CKS_RST_EN_REG4_WR_MASK);
CKS_CLK_SEL_REG1 =(CKS_CLK_SEL_REG1_RES_VAL & CKS_CLK_SEL_REG1_WR_MASK);
CKS_CLK_SEL_REG2 =(CKS_CLK_SEL_REG2_RES_VAL & CKS_CLK_SEL_REG2_WR_MASK);
CKS_CLK_SEL_REG3 =(CKS_CLK_SEL_REG3_RES_VAL & CKS_CLK_SEL_REG3_WR_MASK);
CKS_CLK_SEL_REG4 =(CKS_CLK_SEL_REG4_RES_VAL & CKS_CLK_SEL_REG4_WR_MASK);
CKS_CLK_SEL_REG5 =(CKS_CLK_SEL_REG5_RES_VAL & CKS_CLK_SEL_REG5_WR_MASK);
CKS_CLK_SEL_REG6 =(CKS_CLK_SEL_REG6_RES_VAL & CKS_CLK_SEL_REG6_WR_MASK);
CKS_MDM_PDIV_SEL_REG =(CKS_MDM_PDIV_SEL_REG_RES_VAL & CKS_MDM_PDIV_SEL_REG_WR_MASK);
CKS_CLKOFF_EN_REG =(CKS_CLKOFF_EN_REG_RES_VAL & CKS_CLKOFF_EN_REG_WR_MASK);
CKS_PL_CNTL_REG =(CKS_PL_CNTL_REG_RES_VAL & CKS_PL_CNTL_REG_WR_MASK);
CKS_PL_SEL_REG =(CKS_PL_SEL_REG_RES_VAL & CKS_PL_SEL_REG_WR_MASK);
CKS_CALIB_CNTL_REG3 =(CKS_CALIB_CNTL_REG3_RES_VAL & CKS_CALIB_CNTL_REG3_WR_MASK);
CKS_SLP_CLK_CALIB_CYCLES_REG =(CKS_SLP_CLK_CALIB_CYCLES_REG_RES_VAL & CKS_SLP_CLK_CALIB_CYCLES_REG_WR_MASK);
CKS_PMT_SEL_REG =(CKS_PMT_SEL_REG_RES_VAL & CKS_PMT_SEL_REG_WR_MASK);

}

// Setup CKS module (clocks and resets) for generic setup
void WCDMA_CksSetupAllModulesEngageEnablePllRatio(void)
{
int cntr_apll =0;
int cntr_dpll =0;
// Select Clocks
//Enable APLL and then enable DPLL.
CKS_WCDMA_APLL_CNTL_REG = 0x00000002;
//Await lock 100us, hence the counter.
while (cntr_apll <300){
cntr_apll++;
}
CKS_WCDMA_DPLL_CNTL_REG = 0x00012830;
CKS_WCDMA_DPLL_CNTL_REG = 0x80012830;
//Await lock 300us, hence the counter.
while (cntr_dpll <1000) {
cntr_dpll++;
}


CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000602;
CKS_CLK_SEL_REG4 = 0x00000E8A;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}




// Setup CKS module (clocks and resets) for generic setup
void WCDMA_CksSetupAllModulesEngageEnablePll(void)
{
int cntr_apll =0;
int cntr_dpll =0;
// Select Clocks
//Enable APLL and then enable DPLL.
CKS_WCDMA_APLL_CNTL_REG = 0x00000002;
//Await lock 100us, hence the counter.
while (cntr_apll <300){
cntr_apll++;
}
CKS_WCDMA_DPLL_CNTL_REG = 0x00012410;
CKS_WCDMA_DPLL_CNTL_REG = 0x80012410;
//Await lock 300us, hence the counter.
while (cntr_dpll <1000) {
cntr_dpll++;
}


CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000602;
CKS_CLK_SEL_REG4 = 0x00000E8A;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}

void WCDMA_CksJitterTest15m36Dpll(void)
{
//int cntr_apll =0;
int cntr_dpll =0;
// Select Clocks
//Enable APLL and then enable DPLL.
//CKS_WCDMA_APLL_CNTL_REG = 0x00000002;
//Await lock 100us, hence the counter.
//while (cntr_apll <300){
//cntr_apll++;
//}
CKS_WCDMA_DPLL_CNTL_REG = 0x00012410;
CKS_WCDMA_DPLL_CNTL_REG = 0x80012410;
//Await lock 300us, hence the counter.
while (cntr_dpll <1000) {
cntr_dpll++;
}



//
// Select Clocks
//
//changes for the following reg
CKS_CLK_SEL_REG1 = 0x03001011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
//changes here for the following reg.
CKS_CLK_SEL_REG4 = 0x00000664;
CKS_CLK_SEL_REG4 = 0x02000EEC;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}

void WCDMA_CksJitterTest15m36DpllApll(void)
{
int cntr_apll =0;
int cntr_dpll =0;
// Select Clocks
//Enable APLL and then enable DPLL.
CKS_WCDMA_APLL_CNTL_REG = 0x00000002;
//Await lock 100us, hence the counter.
while (cntr_apll <300){
cntr_apll++;
}
CKS_WCDMA_DPLL_CNTL_REG = 0x00012410;
CKS_WCDMA_DPLL_CNTL_REG = 0x80012410;
//Await lock 300us, hence the counter.
while (cntr_dpll <1000) {
cntr_dpll++;
}



//
// Select Clocks
//
//changes for the following reg
CKS_CLK_SEL_REG1 = 0x03001011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
//changes here for the following reg.
CKS_CLK_SEL_REG4 = 0x00000664;
CKS_CLK_SEL_REG4 = 0x02000EEC;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock
CKS_MDM_PDIV_SEL_REG = 0x00000000;
CKS_MDM_PDIV_SEL_REG = 0x00000100;

//
// Setup Punctured Clock Logic and
// Decoder Clock-Off Request
//
// Set Decoder to allow clkoff_req
CKS_CLKOFF_EN_REG = 0x00000001;
// Set Punctured Logic to WCDMA cx32 Mode
CKS_PL_SEL_REG = 0x0000000B;
CKS_PL_CNTL_REG = 0x00000001;
//
// Enable Clocks
//
CKS_CLK_EN_REG1 = 0xFFFFFFFF;
CKS_CLK_EN_REG2 = 0xFFFFFFFF;
CKS_CLK_EN_REG3 = 0xFFFFFFFF;
CKS_CLK_EN_REG4 = 0xFFFFFFFF;
//
// Enable Sleep Mode
//
CKS_SLP_EN_REG1 = 0xFFFFFFFF;
CKS_SLP_EN_REG2 = 0xFFFFFFFF;
CKS_SLP_EN_REG3 = 0xFFFFFFFF;
CKS_SLP_EN_REG4 = 0xFFFFFFFF;
//
// De-assert Resets
//
CKS_RST_EN_REG1 = 0xFFFFFFFF;
CKS_RST_EN_REG2 = 0xFFFFFFFF;
CKS_RST_EN_REG3 = 0xFFFFFFFF;
CKS_RST_EN_REG4 = 0xFFFFFFFF;
//
// We are done setting up the CKS!
//
}

// Setup CKS module (clocks and resets) for generic setup
void WCDMA_CksSetupAllModulesUsePll(void)
{
//
// Select Clocks
//
CKS_CLK_SEL_REG1 = 0x03012011;
CKS_CLK_SEL_REG2 = 0x01222132;
CKS_CLK_SEL_REG3 = 0x22122221;
CKS_CLK_SEL_REG4 = 0x00000602;
CKS_CLK_SEL_REG4 = 0x00000E8A;
CKS_CLK_SEL_REG5 = 0x00040000;
CKS_CLK_SEL_REG5 = 0x800C0002;
CKS_CLK_SEL_REG6 = 0x00000003;

//
// Setup Programmable Dividers and Pulse Swallowers
//
// Set Modem PDIV/PS to Pass-Through DPLL Clock