📄 clkrst.c
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//=======================================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
//
//=======================================================================================
#include "global_types.h"
#include "result.h"
#include "intvecs.h"
#include "clkrst.h"
#include "test.h"
#include "mem.h"
BOOL dpll_locked_flag = FALSE; // indicates DPLL has already been locked at least once
//---------------------------------------------------------------------
// NAME : CLKRST_DpllSetClockAndLock
//
// DESCRIPTION : Modify the value output from dpll
//
// SYNOPSYS : BOOL CLKRST_DpllSetClockAndLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE dpllreglabel)
//
//
// PARAMETERS : multiplier a value which belong : 1-2047
//
// divider a value which belong : 1-32
//
// dpllreglabel DPLL1, DPLL2 or DPLL3
//
// RETURN VALUE: IS_OK if correct NOT_OK if not
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL CLKRST_DpllSetClockAndLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE_t dpllreglabel)
{
UWORD32 i=0;
UWORD16 temp=0;
if ( (dpllreglabel== DPLL1) && dpll_locked_flag ) // software workaround for DPLL initz bug
return(CLKRST_DpllWarmSetClockAndLock(multiplier, divider, DPLL1));
divider--;
if ( (divider<1) && (divider>32) )
return((BOOL)NOT_OK);
if ( (multiplier<1) OR (multiplier>2047) )
return((BOOL)NOT_OK);
switch(dpllreglabel)
{
case DPLL1 :
{
// Load multiplier and divider values
CLKRST_DPLLCTL1 = (multiplier << 5) | divider;
ClearBitIndex(CLKRST_DPLLCTL3, PLL_ENABLE_POS); // clear Enable bit
SetBitIndex(CLKRST_DPLLCTL3, PLL_ENABLE_POS); // set Enable bit
// lock Dpll
SetBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS); // set Initz bit
ClearBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS);// clear Initz bit
SetBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS); // set Initz bit
// wait for DPLL to be locked
while ( !(GetGroupBits16(CLKRST_DPLLCTL3, LOCK_POS, 1)) && (i++<TIMEOUT_LOCK) );
if ( i== TIMEOUT_LOCK ) return((BOOL)NOT_OK);
break;
}
default :
return((BOOL)NOT_OK);
}//end switch
dpll_locked_flag = TRUE;
return((BOOL)IS_OK);
}
//---------------------------------------------------------------------
// NAME : CLKRST_DpllWarmSetClockAndLock
//
// DESCRIPTION : Modify the value output from dpll when DPLL has already been locked previously
//
// SYNOPSYS : BOOL CLKRST_DpllWarmSetClockAndLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE dpllreglabel)
//
//
// PARAMETERS : multiplier a value which belong : 1-2047
//
// divider a value which belong : 1-32
//
// dpllreglabel DPLL1, DPLL2 or DPLL3
//
// RETURN VALUE: IS_OK if correct NOT_OK if not
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL CLKRST_DpllWarmSetClockAndLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE_t dpllreglabel)
{
UWORD32 i=0;
UWORD16 temp=0, ckctl_val;
divider--;
if ( (divider<1) && (divider>32) )
return((BOOL)NOT_OK);
if ( (multiplier<1) OR (multiplier>2047) )
return((BOOL)NOT_OK);
switch(dpllreglabel)
{
case DPLL1 :
{
ckctl_val = CLKRST_ARM_CKCTL; // save CLKRST_ARM_CKCTL original value
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
CLKRST_ARM_CKCTL = 0x1555; // set ARM/DSP/TC clock dividers to DPLL/2
// switch to bypass mode
SetGroupBits16(CLKRST_ARM_SYSST, CLKRST_ARM_SYSST_CLOCK_SELECT_POS, CLKRST_ARM_SYSST_CLOCK_SELECT_NUMB, 0x5);
// Load multiplier and divider values
CLKRST_DPLLCTL1 = (multiplier << 5) | divider;
ClearBitIndex(CLKRST_DPLLCTL3, PLL_ENABLE_POS); // clear Enable bit
SetBitIndex(CLKRST_DPLLCTL3, PLL_ENABLE_POS); // set Enable bit
// lock Dpll
SetBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS); // set Initz bit
ClearBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS);// clear Initz bit
SetBitIndex(CLKRST_DPLLCTL3, PLL_INITZ_POS); // set Initz bit
// wait for DPLL to be locked
while ( !(GetGroupBits16(CLKRST_DPLLCTL3, LOCK_POS, 1)) && (i++<TIMEOUT_LOCK) );
if ( i== TIMEOUT_LOCK ) return((BOOL)NOT_OK);
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
// switch back to scalable mode
SetGroupBits16(CLKRST_ARM_SYSST, CLKRST_ARM_SYSST_CLOCK_SELECT_POS, CLKRST_ARM_SYSST_CLOCK_SELECT_NUMB, 0x2);
// write original value of CLKRST_ARM_CKCTL back
// CLKRST_ARM_CKCTL = ckctl_val;
CLKRST_ARM_CKCTL = 0x5101; // set ARM/DSP/TC clock dividers to DPLL output frequency
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
break;
}
default :
return((BOOL)NOT_OK);
}//end switch
dpll_locked_flag = TRUE;
return((BOOL)IS_OK);
}
//---------------------------------------------------------------------
// NAME : CLKRST_DpllBypass
//
// DESCRIPTION : Switch to OMAP bypass mode
//
// SYNOPSYS : BOOL CLKRST_DpllBypass()
//
// RETURN VALUE: IS_OK if correct NOT_OK if not
//
// LIMITATIONS : None
//
//---------------------------------------------------------------------
BOOL CLKRST_DpllBypass()
{
UWORD16 ckctl_val;
ckctl_val = CLKRST_ARM_CKCTL; // save CLKRST_ARM_CKCTL original value
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
CLKRST_ARM_CKCTL = 0x1555; // set ARM/DSP/TC clock dividers to DPLL/2
// switch to bypass mode
SetGroupBits16(CLKRST_ARM_SYSST, CLKRST_ARM_SYSST_CLOCK_SELECT_POS, CLKRST_ARM_SYSST_CLOCK_SELECT_NUMB, 0x5);
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
asm(" nop");
return((BOOL)IS_OK);
}
//----------------------------------------------------------
// NAME : CLKRST_SetPeripheralClockEnable
// DESCRIPTION : Enable/Disable the selected peripheral clock
//
// PARAMETERS : PerifName
// WDGTIM_CK,
// XORPC_CK,
// PER_CK,
// LCD_CK,
// LB_CK,
// HSAB_CK,
// API_CK,
// TIM_CK,
// DMA_REQ_CK,
// GPIO_CK,
// LBFREE_CK,
// ALL_CK
//
// and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
// NOT_OK if not -
// LIMITATIONS : None -
// ----------------------------------------------------------
BOOL CLKRST_SetPeripheralClockEnable(CLOCK_SWITCH_t PerifName, BOOL State)
{
UWORD16 Pos, Numb,temp;
switch (PerifName)
{
case WDGTIM_CK ://watchdog timer clock
{
Pos=EN_WDTCK_POS;
Numb=EN_WDTCK_NUMB;
break;
}
case XORPC_CK ://vtcxo reference peripheral
{
Pos=EN_XORPCK_POS;
Numb=EN_XORPCK_NUMB;
break;
}
case PER_CK ://external peripheral
{
Pos=EN_PERCK_POS;
Numb=EN_PERCK_NUMB;
break;
}
case LCD_CK ://lcd
{
Pos=EN_LCDCK_POS;
Numb=EN_LCDCK_NUMB;
break;
}
case LB_CK ://LB clock
{
Pos=EN_LBCK_POS;
Numb=EN_LBCK_NUMB;
break;
}
case HSAB_CK ://HSAB clock
{
Pos=EN_HASBCK_POS;
Numb=EN_HASBCK_NUMB;
break;
}
case API_CK ://API clock
{
Pos=EN_APICK_POS;
Numb=EN_APICK_NUMB;
break;
}
case TIM_CK ://os timer
{
Pos=EN_TIMCK_POS;
Numb=EN_TIMCK_NUMB;
break;
}
case DMA_REQ_CK ://DMA clock
{
Pos=DMACK_REQ_POS;
Numb=DMACK_REQ_NUMB;
break;
}
case GPIO_CK ://GPIO clock
{
Pos=EN_GPIOCK_POS;
Numb=EN_GPIOCK_NUMB;
break;
}
case LBFREE_CK ://LBFREE clock
{
Pos=EN_LBFREECK_POS;
Numb=EN_LBFREECK_NUMB;
break;
}
case ALL_CK ://ALL clocks
{
if (State==ENABLE)
{
SetGroupBits16(ARM_IDLECT2_REG,0,11,0xFFFF);
}
else
{
SetGroupBits16(ARM_IDLECT2_REG,0,11,0x0);
}
return((BOOL)TRUE);
}
default :
{
return((BOOL)FALSE);
}
}
temp = ARM_IDLECT2_REG;
SetGroupBits16(temp,Pos,Numb,State);
ARM_IDLECT2_REG= temp;
return((BOOL)TRUE);
}
//----------------------------------------------------------
// NAME : CLKRST_SetDspPeripheralClockEnable
// DESCRIPTION : Enable/Disable the selected peripheral clock
//
// PARAMETERS : PerifName
// DSP_WDGTIM_CK
// DSP_XORPC_CK
// DSP_PER_CK
// DSP_UART_CK
// DSP_GPIO_CK
// DSP_TIM_CK
// DSP_ALL_CK
//
// and State=ENABLE or DISABLE
// RETURN VALUE: IS_OK if the operation succeed
// NOT_OK if not -
// LIMITATIONS : None -
// ----------------------------------------------------------
BOOL CLKRST_SetDspPeripheralClockEnable(DSP_CLOCK_SWITCH_t PerifName, BOOL State)
{
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