uwire.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  //ONCE THE WRITE REQUEST IS DONE
  //
/*   if ( reg_value != 0x4000 ) */
/*   { */
/*        RES_Set(UWIRE_CSR_WRITE_ERROR); */
/*        RES_Set(reg_value); */
/*        err = RES_BAD; */
/*   }//endif  */

  //POLLING CSRB bit
  //When the corresponding action Read or Write is done
  //the CSRB bit is reset
  do
  {
    reg_value = UWIRE_CSR_REG & 0x4000;
  }while ( reg_value != 0x0000 );



  //--------------------------------------
  // 7) Check SR1 WRITTING               -
  //--------------------------------------
  UWIRE_SR1_REG = 0x05a5;
  reg_value = UWIRE_SR1_REG & 0x0fff;
  if ( reg_value != 0x05a5 )
  {
     RES_Set(UWIRE_SR1_WRITE_ERROR);
     RES_Set(reg_value);
     err = RES_BAD;
  }

  //-----------------------------------------
  // 8) Check SR2 WRITTING                  -
  //-----------------------------------------
  UWIRE_SR2_REG = 0x0a5a;
  reg_value = (UWIRE_SR2_REG & 0x0fff);
  if ( reg_value != 0x0a5a )
  {
     RES_Set(UWIRE_SR2_WRITE_ERROR);
     RES_Set(reg_value);
     err = RES_BAD;
  }


  return err;
}


//------------------------------------
//    UWIRE_SetSr1Reg
//------------------------------------
void UWIRE_SetSr1Reg(UWORD16 value)
{
  UWIRE_SR1_REG = value;
}


//------------------------------------
//    UWIRE_SetSr2Reg
//------------------------------------
void UWIRE_SetSr2Reg(UWORD16 value)
{
  UWIRE_SR2_REG = value;
}

//------------------------------------
//    UWIRE_SetCsrReg
//------------------------------------
void UWIRE_SetCsrReg(UWORD16 value)
{
  UWIRE_CSR_REG = value;
}





//----------------------------------------------------------
//   UWIRE_SetupSr1OrSr2
//----------------------------------------------------------
void UWIRE_SetupSr1OrSr2(UWIRE_CsIndex_t index,
                         UWIRE_EdgeRd_t  readEdge,
                         UWIRE_EdgeWr_t  writeEdge,
		         UWIRE_CsLvl_t   CSlevel,
                         UWIRE_CsFrq_t   frequency,
                         UWIRE_CsChk_t   check)
{
UWORD16 uwireSR1;
UWORD16 uwireSR2;

  switch (index)
  {
    case UWIRE_CS0_INDEX:  //Chip Select CS0 is selected
        //Read SR1 register
        uwireSR1 = UWIRE_SR1_REG;
        //Update SR1 register
    	uwireSR1 &= ~UWIRE_EEPROM_MASK;
        uwireSR1 |= ( (readEdge) | (writeEdge << 1) |
		      (CSlevel << 2) | (frequency << 3) |
		      (check << 5) );
        //Commit SR1 Register Update
        UWIRE_SR1_REG = uwireSR1;
	break;

    case UWIRE_CS1_INDEX:  //Chip Select CS1 is selected
        //Read SR1 register
        uwireSR1 = UWIRE_SR1_REG;
        //Update SR1 register
    	uwireSR1 &= ~(UWIRE_EEPROM_MASK << 6);
        uwireSR1 |= ( (readEdge<<6) | (writeEdge << 7) |
		      (CSlevel << 8) | (frequency << 9) |
		      (check << 11) );
        //Commit SR1 Register Update
        UWIRE_SR1_REG = uwireSR1;
	break;

    case  UWIRE_CS2_INDEX:
        //Read SR2 register
        uwireSR2 = UWIRE_SR2_REG;
        //Update SR2 register
    	uwireSR2 &= ~UWIRE_EEPROM_MASK;
        uwireSR2 |= ( (readEdge) | (writeEdge << 1) |
		      (CSlevel << 2) | (frequency << 3) |
		      (check << 5) );
        //Commit SR2 register Update
        UWIRE_SR2_REG = uwireSR2;
	break;

    case UWIRE_CS3_INDEX:
        //Read SR2 register
        uwireSR2 = UWIRE_SR2_REG;
        //Update SR2 register
    	uwireSR2 &= ~(UWIRE_EEPROM_MASK << 6);
        uwireSR2 |= ( (readEdge<<6) | (writeEdge << 7) |
		      (CSlevel << 8) | (frequency << 9) |
		      (check << 11) );
        //Commit SR2 register Update
        UWIRE_SR2_REG = uwireSR2;
	break;

  }//end switch

}



//----------------------------------------------------------
//   UWIRE_Setup3
//-----------------------------------------------------------
void UWIRE_Setup3(UWIRE_ClkEn_t clk_en, UWIRE_ClkFreq_t clk_freq)
{
UWORD16 uwireSR3 = UWIRE_SR3_REG;
  uwireSR3 = 0;
  uwireSR3 |= ((clk_en) | (clk_freq << 1));

  UWIRE_SR3_REG = uwireSR3;
}

// Some actions of the uwire start by setting a bit in the CSR_REG
// Any writting and action will set and keep the CSRB bit to 1 till the end of
// the writting or the end of the action . It is an hardware action cloked by the uwire
// clock.
// The problem to do a polling on this bit at the beginning of a new function
//( a new action ) depends of the code fetching speed . If the fetching speed is high
// then we can start the polling on the CSRB in the next function even before the
// setting of CSRB by the hardware ond so we shunt one action.
// To avoid that we keep the hand till the action is finished by doing a polling on
// the CSRB . The limitating factor is the time between the reading of the CSR_REG and the
// test on the CSRB. To have this time the shortest than possible and to control it well
// the sequence is coded straight in assembly code.
// BUT IT IS  REQUIRED that this arm code  RUNS IN THUMB CODE MODE.
//

//-----------------------------------------------------------
//   UWIRE_Select  
//-----------------------------------------------------------
void UWIRE_Select(UWIRE_Index_t cs_index)
{  
UWORD16 uwireCSR;
  do {
     uwireCSR = UWIRE_CSR_REG;
  } while (uwireCSR & UWIRE_CSR_CSRB_MASK);

  uwireCSR &= ~UWIRE_CSR_ERASE_MASK;
  // uwireCSR |= (CSR_CS_CMD_MASK | (index << 9));  old with error
  // set Chip Select and index  
  uwireCSR |= (UWIRE_CSR_CS_CMD_MASK | ((UWORD16)cs_index << 10));
  //Commit the Update
  UWIRE_CSR_REG = uwireCSR;
}	
 
//-----------------------------------------------------------
//   UWIRE_ActivatePeriph
//-----------------------------------------------------------
void UWIRE_ActivatePeriph(void)
{
UWORD16 uwireCSR;
  do {
     uwireCSR = UWIRE_CSR_REG;
  } while (uwireCSR & UWIRE_CSR_CSRB_MASK);

  // set Chip Select and index
  uwireCSR |= UWIRE_CSR_CS_CMD_MASK ;

  //WAIT END OF THE CS update

  asm(" mov r0, SP ");

  //load value of the C variable uwireCSR in R1
  asm(" ldr r1,[r0] " );

  //mask for the CSRB bit field
  asm(" mov r3, #0x1");

  asm(" lsl r3, r3, #14 ");

  //load adress of the CSR_REG in r6
  asm(" mov r5, #0x4d ");

  asm(" lsl r5, r5, #12 ");

  asm(" mvn r6, r5 ");

  asm(" add r6, #0x5 ");

  //store the value of the c variable uwireCSR in CSR_REG of the uwire
  asm(" str r1,[r6]");

  //load the value of the uwire CSR_REG
  asm(" ldr r1,[r6]");

  //mask all the bit except the CSRB bit field and store the result in r1
  //if CSRB = 1 then flag Z =0 else Z=1
  asm(" and r1, r3 ");

  //branch if flag Z = 1 to asm(" ldr r1,[r6]")
  asm(" beq #-0x8 ");

}

//-----------------------------------------------------------
//   UWIRE_DeactivatePeriph
//-----------------------------------------------------------
void UWIRE_DeactivatePeriph(void)
{
UWORD16 uwireCSR;
  do {
     uwireCSR = UWIRE_CSR_REG;
  } while (uwireCSR & UWIRE_CSR_CSRB_MASK);

  // set Chip Select and index
  uwireCSR &= ~UWIRE_CSR_CS_CMD_MASK ;

  //WAIT END OF THE CS update

  asm(" mov r0, SP ");

  //load value of the C variable uwireCSR in R1
  asm(" ldr r1,[r0] " );

  //mask for the CSRB bit field
  asm(" mov r3, #0x1");

  asm(" lsl r3, r3, #14 ");

  //load adress of the CSR_REG in r6
  asm(" mov r5, #0x4d ");

  asm(" lsl r5, r5, #12 ");

  asm(" mvn r6, r5 ");

  asm(" add r6, #0x5 ");

  //store the value of the c variable uwireCSR in CSR_REG of the uwire
  asm(" str r1,[r6]");

  //load the value of the uwire CSR_REG
  asm(" ldr r1,[r6]");

  //mask all the bit except the CSRB bit field and store the result in r1
  //if CSRB = 1 then flag Z =0 else Z=1
  asm(" and r1, r3 ");

  //branch if flag Z = 1 to asm(" ldr r1,[r6]")
  asm(" beq #-0x8 ");

}


///----------------------------------------------------------
//   UWIRE_Release  
//----------------------------------------------------------
void UWIRE_Release(void)
{  
UWORD16 uwireCSR;
  do {
    uwireCSR = UWIRE_CSR_REG;
  } while (uwireCSR & UWIRE_CSR_CSRB_MASK);

  // Unset Chip Select  
  uwireCSR &= ~UWIRE_CSR_CS_CMD_MASK;
  //Commit Register Update
  UWIRE_CSR_REG = uwireCSR;
}	


//-----------------------------------------------------------
//   UWIRE_Write 
//-----------------------------------------------------------
void UWIRE_Write(UWORD16 data, UWORD8 write_len, UWORD8 read_len)
{  
UWORD16 uwireCSR;
  // wait Control Status register ready to receive new data
  do 
  {
    //Set uwireCSR to Control & status register's contents
    uwireCSR = UWIRE_CSR_REG;
  } while(uwireCSR & UWIRE_CSR_CSRB_MASK);

   // load transmit register
   UWIRE_TDR_REG = data;
	
   // erase previous lengths
   uwireCSR &= ~UWIRE_CSR_NB_BITS_RD_WR_MASK;
   // set bits nb and start
   uwireCSR |= (read_len | (write_len << 5) | UWIRE_CSR_START_MASK);