uwire.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================
//       TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 2000,(C) Copyright 2000 Texas Instruments.
// All rights reserved.
//
//   Filename       	: uwire.c
//
//   Description    	: Set of functions useful to test the MICROWIRE
//			  interface of DIONE
//
//   Project        	: samsom
//
//   Author         	: Francois Reygagne [e-mail]
//                                    modify by Serge Imbert [e-mail] 11/29/2000
//---------------------------------------------------------------------------

#include "test.h"
#include "global_types.h"
#include "result.h"
#include "intvecs.h"
#include "uwire.h"
#include "result.h"
#include "reset.h"
#include "errorcodes.h"


// Some actions of the uwire start by setting a bit in the CSR_REG
// Any writting and action will set and keep the CSRB bit to 1 till the end of
// the writting or the end of the action . It is an hardware action cloked by the uwire
// clock.
// The problem to do a polling on this bit at the beginning of a new function
//( a new action ) depends of the code fetching speed . If the fetching speed is high
// then we can start the polling on the CSRB in the next function even before the
// setting of CSRB by the hardware ond so we shunt one action.
// To avoid that we keep the hand till the action is finished by doing a polling on
// the CSRB . The limitating factor is the time between the reading of the CSR_REG and the
// test on the CSRB. To have this time the shortest than possible and to control it well
// the sequence is coded straight in assembly code.
// BUT IT IS  REQUIRED that this arm code  RUNS IN THUMB CODE MODE.
//



void UWIRE_TestResetValue(void)
{

  UWIRE_SR3_REG|=0x1;
  READ_ACCESS_WORK_WITH_REGISTER(&UWIRE_CSR_REG,16)
    TEST_FIELD_RES_VAL(CS_CMD,16);
    TEST_FIELD_RES_VAL(START,16);
    TEST_FIELD_RES_VAL(CSRB,16);
    TEST_FIELD_RES_VAL(RDRB,16);
  END;

  TEST_FIELD_RESET_VALUE(&UWIRE_SR1_REG,CS0CS_LVL);
  TEST_FIELD_RESET_VALUE(&UWIRE_SR1_REG,CS1CS_LVL);

  TEST_FIELD_RESET_VALUE(&UWIRE_SR2_REG,CS2CS_LVL);
  TEST_FIELD_RESET_VALUE(&UWIRE_SR2_REG,CS3CS_LVL);

  TEST_FIELD_RESET_VALUE(&UWIRE_SR4_REG,CLK_IN);

  PRINT_CURRENT_ERROR_STATUS(UWIRE_TEST_RESET_VALUE_SUCCEEDED);
}

void UWIRE_TestRegistersAccess(void)
{
  UWIRE_SR3_REG|=0x1;
  READWRITE_ACCESS_WORK_WITH_REGISTER(&UWIRE_CSR_REG,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(UWIRE_CSR_NBBITSRD,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(UWIRE_CSR_NBBITSWR,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(UWIRE_CSR_INDEX,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CS_CMD,16);

    /* THIS BIT IS READ ONLY */
   /* READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CSRB,16);*/

    /* DO NOT MODIFY THIS START TRNSMISSION PROCESS BIT */
   /* READWRITE_ACCESS_PREPARE_OPPOSED_MASK(START,16);*/

    WRITE_MASK(&UWIRE_CSR_REG,16);

    /*READ_WRITE_CHECK_TEST_FIELD(START,16); */
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(UWIRE_CSR_NBBITSRD,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(UWIRE_CSR_NBBITSWR,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(UWIRE_CSR_INDEX,16);
    READ_WRITE_CHECK_TEST_FIELD(CS_CMD,16);

    /*READ_WRITE_CHECK_TEST_FIELD(CSRB,16);*/

    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(UWIRE_CSR_NBBITSRD,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(UWIRE_CSR_NBBITSWR,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(UWIRE_CSR_INDEX,16);

    WRITE_MASK(&UWIRE_CSR_REG,16);

    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(UWIRE_CSR_NBBITSRD,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(UWIRE_CSR_NBBITSWR,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(UWIRE_CSR_INDEX,16);

    WRITE_PREVIOUS_VALUE(&UWIRE_CSR_REG,16);
  END;


  READWRITE_ACCESS_WORK_WITH_REGISTER(&UWIRE_SR1_REG,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS0_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS0_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS0_FRQ,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS0_CHK,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS1_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS1_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS1_FRQ,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS1_CHK,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CS0CS_LVL,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CS1CS_LVL,16);

    WRITE_MASK(&UWIRE_SR1_REG,16);

    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS0_EDGE_RD,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS0_EDGE_WR,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS0_FRQ,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS0_CHK,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS1_EDGE_RD,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS1_EDGE_WR,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS1_FRQ,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS1_CHK,16);
    READ_WRITE_CHECK_TEST_FIELD(CS0CS_LVL,16);
    READ_WRITE_CHECK_TEST_FIELD(CS1CS_LVL,16);

    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS0_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS0_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS0_FRQ,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS0_CHK,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS1_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS1_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS1_FRQ,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS1_CHK,16);

    WRITE_MASK(&UWIRE_SR1_REG,16);

    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS0_EDGE_RD,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS0_EDGE_WR,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS0_FRQ,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS0_CHK,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS1_EDGE_RD,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS1_EDGE_WR,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS1_FRQ,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS1_CHK,16);

    WRITE_PREVIOUS_VALUE(&UWIRE_SR1_REG,16);
  END;


  READWRITE_ACCESS_WORK_WITH_REGISTER(&UWIRE_SR2_REG,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS2_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS2_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS2_FRQ,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS2_CHK,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS3_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS3_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS3_FRQ,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CS3_CHK,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CS2CS_LVL,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CS3CS_LVL,16);

    WRITE_MASK(&UWIRE_SR2_REG,16);

    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS2_EDGE_RD,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS2_EDGE_WR,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS2_FRQ,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS2_CHK,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS3_EDGE_RD,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS3_EDGE_WR,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS3_FRQ,16);
    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CS3_CHK,16);
    READ_WRITE_CHECK_TEST_FIELD(CS2CS_LVL,16);
    READ_WRITE_CHECK_TEST_FIELD(CS3CS_LVL,16);

    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS2_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS2_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS2_FRQ,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS2_CHK,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS3_EDGE_RD,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS3_EDGE_WR,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS3_FRQ,16);
    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CS3_CHK,16);

    WRITE_MASK(&UWIRE_SR2_REG,16);

    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS2_EDGE_RD,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS2_EDGE_WR,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS2_FRQ,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS2_CHK,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS3_EDGE_RD,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS3_EDGE_WR,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS3_FRQ,16);
    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CS3_CHK,16);

    WRITE_PREVIOUS_VALUE(&UWIRE_SR2_REG,16);
  END;


  READWRITE_ACCESS_WORK_WITH_REGISTER(&UWIRE_SR3_REG,16);
    READWRITE_ACCESS_PREPARE_FIRST_UNDEFINED_MASK(CK_FREQ,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CLK_IN,16);
    READWRITE_ACCESS_PREPARE_OPPOSED_MASK(START,16);
    /*READWRITE_ACCESS_PREPARE_OPPOSED_MASK(CLK_EN,16);*/

    WRITE_MASK(&UWIRE_SR3_REG,16);

    READ_WRITE_CHECK_FIRST_UNDEFINED_TEST_FIELD(CK_FREQ,16);
    READ_WRITE_CHECK_TEST_FIELD(CLK_IN,16);
    READ_WRITE_CHECK_TEST_FIELD(START,16);
    /*READ_WRITE_CHECK_TEST_FIELD(CLK_EN,16);*/

    READWRITE_ACCESS_PREPARE_SECOND_UNDEFINED_MASK(CK_FREQ,16);

    WRITE_MASK(&UWIRE_SR3_REG,16);

    READ_WRITE_CHECK_SECOND_UNDEFINED_TEST_FIELD(CK_FREQ,16);

    WRITE_PREVIOUS_VALUE(&UWIRE_SR3_REG,16);
  END;


  PRINT_CURRENT_ERROR_STATUS(UWIRE_TEST_REGISTER_ACCESS_SUCCEEDED);
}





//--------------------------------------------------------------------------------
//	NAME 		: UWIRE_TestRegisters
//---------------------------------------------------------------------------------
UWORD8 UWIRE_TestRegisters(void)
{
UWORD16 reg_value;
//Global status: 0 on success otherwise 1
UWORD8 err=RES_OK;

//--------------------------------------------------
// CHECK DEFAULT REGISTERS VALUE ON RESET          -
//--------------------------------------------------

  //1) Check Control & Status Register reset value
  //--------------------------------------------------

  reg_value = UWIRE_CSR_REG & UWIRE_CSR_REG_RESET_MASK;

  if ( reg_value != UWIRE_CSR_REG_RESET_VALUE )
  {
       RES_Set(UWIRE_CSR_RESET_ERROR);
       RES_Set(reg_value);
       err = RES_BAD;
  }//endif


  //2) Check Setup Register 1  reset value
  //--------------------------------------------------------
  reg_value = UWIRE_SR1_REG & UWIRE_SR1_REG_RESET_MASK;
  if ( reg_value != UWIRE_SR1_REG_RESET_VALUE )
  {
       RES_Set(UWIRE_SR1_RESET_ERROR);
       RES_Set(reg_value);
       err = RES_BAD;
  }//endif Setup Register1

  //3) Check Setup Register 2  reset value
  //-----------------------------------------------------------
  reg_value = UWIRE_SR2_REG & UWIRE_SR2_REG_RESET_MASK;
  if ( reg_value != UWIRE_SR2_REG_RESET_VALUE )
  {
       RES_Set(UWIRE_SR2_RESET_ERROR);
       RES_Set(reg_value);
       err = RES_BAD;
  }//endif Setup Register2

  // 4) Check Setup Register 3 reset value
  //----------------------------------------------------------
  reg_value = UWIRE_SR3_REG & UWIRE_SR3_REG_RESET_MASK;
  if ( reg_value != UWIRE_SR3_REG_RESET_VALUE )
  {
       RES_Set(UWIRE_SR3_RESET_ERROR);
       RES_Set(reg_value);
       err = RES_BAD;
  }//endif Setup Register3


  //---------------------------
  // 5) Check SR3 WRITTING    -
  //---------------------------

  //Write a value into Register SR3
  UWIRE_SR3_REG = 0x0005;
  //Read back the Register SR3
  reg_value = UWIRE_SR3_REG & UWIRE_SR3_MASK;
  //Check if the read value matches the written value
  if ( reg_value != 0x0005 )
  {
     RES_Set(UWIRE_SR3_WRITE_ERROR);
     RES_Set(reg_value);
     err = RES_BAD;
  }

  //---------------------------------------------
  // 6) Check CSR WRITTING & CSRB bit Setting   -
  //---------------------------------------------
  //Activate chip_select of the selected device
  //and Start a Write/Read Process
  UWIRE_CSR_REG = 0x1000;

  //Reset the CSR REG
  UWIRE_CSR_REG = UWIRE_CSR_REG_RESET_VALUE;
  //Check manually that the CSRB bit is set to 1 and
  //is reset immediatly by the termination
  //of the Chip Select Setting

  reg_value = UWIRE_CSR_REG & UWIRE_CSR_REG_RESET_MASK;

  //The CSRB bit must be set to 1 just after writting
  //into the Ctrol & Status Register (CSRB), either
  //the CS_CMD or the START bit.
  //PUT IN COMMENT SINCE THIS BIT IS RESET TOO FAST