gdma.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

    case (DMA_CHANNEL_1) : // Physical channel 1, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH1,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH1, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH1
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH1);

      break;
    }

    case (DMA_CHANNEL_2) : // Physical channel 2, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH2,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH2, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH2
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH2);

      break;
    }

    case (DMA_CHANNEL_3) : // Physical channel 3, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH3,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH3, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH3
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH3);

      break;
    }

    case (DMA_CHANNEL_4) : // Physical channel 4, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH4,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH4, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH4
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH4);

      break;
    }

    case (DMA_CHANNEL_5) : // Physical channel 5, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH5,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH5, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH5
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH5);

      break;
    }

    case (DMA_CHANNEL_6) : // Physical channel 6, Logical channel 0
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH0,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH0, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH0
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH0);

      break;
    }

    case (DMA_CHANNEL_7) : // Physical channel 7, Logical channel 1
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH1,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH1, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH1
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH1);

      break;
    }

    case (DMA_CHANNEL_8) : // Physical channel 8, Interrupt channel 2
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH2,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH2, // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH2
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH2);

      break;
    }

    default : 
    {
      break;
    }
  } // of switch

    // RES_StopVhdl();   
}

//-------------------------------------------------------------------------------
// NAME         : DMA_DisableInt 
//
// DESCRIPTION  : Disable the DMA interrupts after the transfer
//
// PARAMETERS  :     ChannelNumb      DMA_CHANNEL_0
//                                    DMA_CHANNEL_1
//                                    DMA_CHANNEL_2
//                                    DMA_CHANNEL_3
//                                    DMA_CHANNEL_4
//                                    DMA_CHANNEL_5
//                                    DMA_CHANNEL_6
//                                    DMA_CHANNEL_7
//                                    DMA_CHANNEL_8
//
// RETURN VALUE : None
//
//-------------------------------------------------------------------------------- 
void DMA_DisableInt(UWORD16 ChannelNumb) 
{
  // disable IRQ for the channel
  //---------------------------------
  switch (ChannelNumb)
  {
    case (DMA_CHANNEL_0) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH0);
      break;
    }
    case (DMA_CHANNEL_1) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH1);
      break;
    }
    case (DMA_CHANNEL_2) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH2);
      break;
    }
    case (DMA_CHANNEL_3) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH3);
      break;
    }
    case (DMA_CHANNEL_4) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH4);
      break;
    }
    case (DMA_CHANNEL_5) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH5);
      break;
    }
    case (DMA_CHANNEL_6) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH0);
      break;
    }
    case (DMA_CHANNEL_7) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH1);
      break;
    }
    case (DMA_CHANNEL_8) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH2);
      break;
    }
    default : 
    {
      break;
    }
  }
}

//-------------------------------------------------------------------------------
// NAME         : DMAT_ConfigPort       
//
// DESCRIPTION  : Setup port configuration involved with data in the channel
//                
//
// PARAMETERS   : ChannelNumber       DMA_CHANNEL_0   
//                                    DMA_CHANNEL_1   
//                                    DMA_CHANNEL_2   
//                                    DMA_CHANNEL_3   
//                                    DMA_CHANNEL_4   
//                                    DMA_CHANNEL_5   
//                                    DMA_CHANNEL_6   
//                                    DMA_CHANNEL_7   
//                                    DMA_CHANNEL_8   
//
//                   SrcPort          DMA_SDRAM    
//                                    DMA_EMIF     
//                                    DMA_IMIF     
//                                    DMA_RHEA     
//                                    DMA_LOCAL    
//                                    DMA_RHEA_API 
//                                    
//                   SrcAdd           Address of the source
//
//                   DestPort         see SrcPort
//
//                   DestAdd          Address of the destination
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
void DMA_ConfigPort(	UWORD32 ChannelNumber,
						UWORD32 SrcPort,
						UWORD32 SrcAdd,
						UWORD32 DestPort,
						UWORD32 DestAdd)
{
CHANNEL_DESCRIPTOR* Chptr;

  if (ChannelNumber == DMA_CHANNEL_LCD)
    {
     return;
    }

    Chptr=&(SystemDma.DmaChannel[ChannelNumber]);
     //DMA Channel Number
     //--------------------
     Chptr->ChannelNumb = ChannelNumber;
		
     //DMA Source
     //--------------------
     Chptr->SrcPort = SrcPort;
     Chptr->SrcAdd = SrcAdd;

     //DMA Destination
     //--------------------
     Chptr->DestPort = DestPort;
     Chptr->DestAdd = DestAdd;
}

//-------------------------------------------------------------------------------
// NAME         : DMA_GetCondBitsInterrupt       
// DESCRIPTION  : Get back the condition bits of the specified channel
// PARAMETERS   : ChannelNumber       DMA_CHANNEL_0   
//                                    DMA_CHANNEL_1   
//                                    DMA_CHANNEL_2   
//                                    DMA_CHANNEL_3   
//                                    DMA_CHANNEL_4   
//                                    DMA_CHANNEL_5   
//                                    DMA_CHANNEL_6   
//                                    DMA_CHANNEL_7   
//                                    DMA_CHANNEL_8   
//                                    DMA_CHANNEL_LCD
// RETURN VALUE : None
//--------------------------------------------------------------------------------
UWORD32 DMA_GetInterrupt(UWORD16 ChannelNumber)
{
UWORD32 Temp;

	//DMA_CSR
	//----------
    Temp=DMA_ACC(NO_GLOB_REG, ChannelNumber, DMA_CSR);
    return(Temp);
}

//-------------------------------------------------------------------------------
// NAME         : DMA_LcdConfigPort
//
// DESCRIPTION  : Setup lcd channel port configuration
//
// PARAMETERS   : SrcPort          DMA_LCD_SDRAM_SRC  
//                                 DMA_LCD_IMIF_SRC   
//
//                AddTop1          Start address of the source for the 1st frame
//                AddBot1          End address of the source for the 1st frame
//
//                AddTop2          Start address of the source for the 2nd frame
//                AddBot2          End address of the source for the 2nd frame
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
void DMA_LcdConfigPort(UWORD32 SrcPort,
			   UWORD32 AddTop1,
			   UWORD32 AddBot1,
			   UWORD32 AddTop2,
			   UWORD32 AddBot2)
{
LCD_CHANNEL_DESCRIPTOR* Chptr;

  Chptr=&(SystemDma.LcdChannel);
		
  //DMA Source
  //--------------------
  Chptr->LcdSrc = SrcPort;

  //DMA Address
  //--------------------
  Chptr->LcdTopF1 = AddTop1;
  Chptr->LcdBotF1 = AddBot1;
  Chptr->LcdTopF2 = AddTop2;
  Chptr->LcdBotF2 = AddBot2;
}
//-------------------------------------------------------------------------------
// NAME         : DMA_LcdFrameMode
//
// DESCRIPTION  : Setup lcd channel frame mode
//
// PARAMETERS   : FrMode	DMA_LCD_FRAMEMODE_ONEFRAME
//				DMA_LCD_FRAMEMODE_TWOFRAME
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
void DMA_LcdFrameMode(UWORD32 FrMode)
{
LCD_CHANNEL_DESCRIPTOR* Chptr;

  Chptr=&(SystemDma.LcdChannel);
		
  //DMA FrameMode
  //--------------------
  Chptr->FrameMode = FrMode;
}