w_8_16_32.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments 
;   For  Unrestricted  Internal  Use  Only
;   Unauthorized reproduction and/or distribution is strictly prohibited.  
;   This product is protected under copyright law and trade secret law 
;   as an unpublished work.	
; 
;   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
;
;
;   Filename     : w_8_16_32.asm
;
;   Description : Test of memory access by byte, half word and word 
;                 (no byte inversion)
;
;   Project     : Satustar
;
;   Author      : [e-mail]  Francois Reygagne.
; 
;******************************************************************************* 
	.state16		; thumb mode

	.ref	edata		;defined by armas
	.global $w_8_16_32
	.ref    etext


OK		.equ  0x0001
BAD		.equ  0x0002
NOT_TESTED	.equ  0x0 
THE_END		.equ  0xffff	;That's the end of the test(s)


 	
$w_8_16_32:           
;
;	- write a word by word, half word and byte
;	- in each case, re-read it by word, half word and byte
;	- and check that the value is correct
;
;	The 3 words are written to the start, middle and end of the memory
;	space given in argument.
;
;	Input : R0 = start address, R1 = length of the memory space
;
;	Output : R0 = result (1 for OK, 2 for bad)
;

	push	{r4,lr}

;Load into R2 address of abcd variable
	ldr	r2,abcd_addr			; R2 = abcd_addr
;Load into R2 contents of abcd_addr i.e 'abcd' 	
	ldr	r2,[r2,#0]			; R2 = 'abcd'

;; -------------------------------------------------------------------------
;  TEST WRITE 32 (start address) Write 'abcd' into memory at Addrcs0      --
;; -------------------------------------------------------------------------
	;Store R2 ('abcd') at the address contained by R0
	str	r2,[r0,#0]	;[R0] := 'abcd' 
	bl	read_back	;Unconditionally branch to 'read_back'
	cmp	r3,#OK		;Compare Result R3 to OK
	bne	its_bad		;IF Result Not OK THEN BRANCH to 'its_bad'
	
;; ---------------------------------------------------------------------------
;; TEST WRITE 16 (middle address)                                           --
;; ---------------------------------------------------------------------------
	lsr	r1,r1,#1		;divide length by 2
	add	r0,r0,r1		;add it to the start address

	; Address must be multiple of 4 bytes (32 bits)
;	ldr	r4,clearmask_addr
;	ldr	r4,[r4,#0]	;Load clearmask into R2
	ldr	r4,clearmask
	bic	r0,r4		;Ro = R0 and not clearmask

	strh	r2,[r0,#0]	;Store 2 bytes 'ab' into middle address
	mov	r4,r2		;R4 = R2 = 'abcd'
	lsr	r4,r4,#16	;Half-Word Shift Right => R4 = 'cd'
	strh	r4,[r0,#2]	;Store 2 bytes 'cd' into middle address+2
	bl	read_back	;Unconditionally branch to 'read_back'
	cmp	r3,#OK		;Compare Result R3 to OK
	bne	its_bad		;IF Result Not OK THEN BRANCH to 'its_bad'
	
;; -------------------------------------------------------------------------
;; TEST WRITE 8 (end address)                                             --
;; -------------------------------------------------------------------------
	add	r0,r0,r1	;R0 = Middle_Address + Half-Length
				;that's the end address
	;WARNING: Address must not be out of bounds
	;to prevent from OUT OF RANGE ERROR
	sub	r0,r0,#4	;R0 = R0 - 4

	; Address must be multiple of 4 bytes (32 bits)
;	ldr	r4,clearmask_addr
;	ldr	r4,[r4,#0]	;Load clearmask into R2
; FH modif
	ldr	r4,clearmask
	bic	r0,r4		;Ro = R0 and not clearmask
	
	mov	r4,r2		;R4='abcd'
	
	strb	r4,[r0,#0]	;Store byte 'a' into end address
	lsr	r4,r4,#8	;Byte Shift Right => 'a' thrown away right
				;and 'b' becomes the first LSB byte
	
	strb	r4,[r0,#1]	;Store byte 'b' into end address+1
	lsr	r4,r4,#8	;Byte Shift Right => 'b' thrown away right
				;and 'c' becomes the first LSB byte
	
	strb	r4,[r0,#2]	;Store byte 'c' into end address+2
	lsr	r4,r4,#8	;Byte Shift Right => 'c' thrown away right
				;and 'd' becomes the first LSB byte
	
	strb	r4,[r0,#3]	;Store byte 'd' into end address+3
	
	bl	read_back	;Unconditionally branch to 'read_back'
	cmp	r3,#OK		;Compare Result R3 to OK
	bne	its_bad		;IF Result Not OK THEN BRANCH to 'its_bad'

its_ok:	
	mov	r0,#OK			;test is ok
	b	the_end			;Unconditionally branch to 'the_end'

its_bad:
	mov	r0,#BAD			;test is bad

the_end:	
	pop 	{r4,pc}		; Return to caller


end:	b 	end		;infinite loop to terminate execution
loop:	b 	loop		; loop to prevent bad execution of data
;
;	Test a write (by reading it back by word, half word and byte)
;
;	R0 = address (preserved)
;	R1 = not used (preserved)
;	R2 = 'abcd' used as a reference (preserved)
;	R3 = returned value (not preserved)
;
read_back:
	;; Read Back by WORD
	ldr	r3,[r0,#0]	;Load word 'abcd' into R3
	cmp	r3,r2		;Set condition codes on result of R3 - R2
	bne	one_bad		;If Read_Data(R3) NotEqual Written_Data(R2) 
				;Branch to 'one_bad' 

	;; Read Back by HALF-WORD
	ldrh	r3,[r0,#0]	;Load half-word 'ab' into R3
	ldrh	r4,[r0,#2]	;Load half-word 'cd' into R4
	lsl	r4,r4,#16	;Shift left R4 to Upper Half-Word
	orr	r3,r4		;Concatenate two half-word => R3 = 'abcd'
	cmp	r3,r2		;Set condition codes on result of R3 - R2
	bne	one_bad		;If Read_Data(R3) NotEqual Written_Data(R2) 
				;Branch to 'one_bad' 

	;; Read Back by BYTE
	ldrb	r3,[r0,#0]	;Load byte 'a' into R3
	ldrb	r4,[r0,#1]	;Load byte 'b' into R4
	lsl	r4,r4,#8	;Shift left 'b' to 2nd byte of R4
	orr	r3,r4		;Setup 2Nd byte of R4 into R3 (R3='ab')
	
	ldrb	r4,[r0,#2]	;Load byte 'c' into R4
	lsl	r4,r4,#16	;Shift left 'c' to 3Rd byte of R4
	orr	r3,r4		;Setup 3Rd byte of R4 into R3 (R3='abc')
	
	ldrb	r4,[r0,#3]	;Load byte 'd' into R4
	lsl	r4,r4,#24	;Shift left 'd' to 4Th byte of R4 
	orr	r3,r4		;Setup 4Rd byte of R4 into R3 (R3='abcd')
	
	cmp	r3,r2		;Set condition codes on result of R3 - R2
	bne	one_bad		;If Read_Data(R3) NotEqual Written_Data(R2) 
				;Branch to 'one_bad' 
one_ok:	
	mov	r3,#OK		;test is ok
	b	one_end		;Unconditionally branch to 'one_end'

one_bad:
	mov	r3,#BAD		;test is bad

one_end:
	mov	pc,lr

	.align 	4
	; select 32 bit instructions assembling mode
	.state32


;;**********************************************************************
;;                   V A R I A B L E S                                **
;;**********************************************************************
abcd_addr  	.word   abcd
abcd	   	.word   'abcd'

;clearmask_addr  .word   clearmask
clearmask		 .word   3 ;mask bit 0 & 1

;
;	Addresses in the data space
;


Addrcs0		.word	etext		;address of ncs0 
Addrcs0end  	.word   0x01ffffff	;32Mb - etext
ad_memif	.word   0xfffefb00	;address of memory interface
Offset_CfgnCS0  .word   0x101c		;offset of nCS0 config register
Offset_Fclk	.word   0x0c		;offset of nCS0 interface config register

		.end			; Terminate assembly