📄 ms.c
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// Read the RxData
RxData = REGU32(MS_RX_DATA_REG_SUPERVISOR_ADDR);
// Check if TxData == RxData, and if no CRC error
// Returns True if both are OK, else False
ok &= (TxData == RxData);
ok &= ((REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) & 0x0002) == 0x0000);
return(ok);
}
//---------------------------------------------------------------------------
// MS_TxRxTestInterruptStart
//---------------------------------------------------------------------------
// 24 bytes loop test with STUB based on INT. Tx FIFO is filled with 8 bytes
// at the begining and ISR serves to write data into FIFO, 8 bytes at each
// call. For Rx, ISR serves to read data from FIFO, 8 bytes at each call.
// Care must be taken at the end of Rx. There are remaining data that are
// not yet read by ISR, it is CPU responsibility to take care of them.
// Note that 24 bytes plus 2 CRC bytes!!
//---------------------------------------------------------------------------
BOOL MS_TxRxTestInterruptStart(void)
{
BOOL ok = True;
UWORD16 i, num;
// Init pointers
RxDataTableAdd = &RxDataTable[0];
TxDataTableAdd = &TxDataTable[0];
// Module Reset
MS_MrstBitValueAtReset();
// Set the Interrupt condition
// TxFIFO Thershold (4bytes) and RxFIFO thershold (12bytes)
REGU16(MS_FIFO_CTL_REG_SUPERVISOR_ADDR) |= 0x0026;
// Enable I/F and select MSByte first mode
REGU16(MS_CNTL_REG_SUPERVISOR_ADDR) |= 0x8020;
// Write the FirstTxData to MSTXDATA Register, total 8bytes
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = *TxDataTableAdd++;
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = *TxDataTableAdd++;
// Enable to send IRQ signal to INTH2 and IRQ to be generated when FIFO cond is met
REGU16(MS_I_CTL_REG_SUPERVISOR_ADDR) |= 0x00c0;
// Tx Protocol Part
// Wait the BS's condition good
while ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0300) != 0x0000)
{
}
// Set the TPC command to write mode and
// and Set the Number of TxByte (24bytes)
REGU16(MS_CMD_REG_SUPERVISOR_ADDR) = 0xb018; // Start Tx
// Wait the BS's condition good
while ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0300) != 0)
{
}
// Rx Protocol Part
// Set the TPC command to read mode and
// set the number of RxByte (24bytes)
REGU16(MS_CMD_REG_SUPERVISOR_ADDR) = 0x4018; // Start Rx
// Wait for end of Rx protocol
while ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0300) != 0)
{
}
// Read rest of Bytes in RxFIFO
num = REGU16(MS_FIFO_CNT_REG_SUPERVISOR_ADDR) & 0x00ff;
for(i=0; i<(num/4); i++)
{
// Read the RxData
*RxDataTableAdd++ = REGU32(MS_RX_DATA_REG_SUPERVISOR_ADDR);
}
// Compare Txed and Rxed data
for (i=0; i<6; i++)
{
ok &= (TxDataTable[i] == RxDataTable[i]);
}
// Check CRC
ok &= ((REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) & 0x0002) == 0x0000);
return(ok);
}
//---------------------------------------------------------------------------
// MS_TxRxIntIsr
//---------------------------------------------------------------------------
// ISR for INT based loop test. If tx, it writes 8 bytes data into FIFO at
// each call. If Rx, it reads 8 bytes data from FIFO at each call. It also
// take care of RDY INT clear.
//---------------------------------------------------------------------------
void MS_TxRxIntIsr(void)
{
UWORD16 i;
UWORD16 temp;
// Check the type of Interrupt that is received now
// If that is Data request interrupt is asserted
// then do the following command,else finished this function
if ((REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) & 0x0020) == 0x0020)
{
// If this interrupt is for Tx then write 8bytes TxData to TxRegister
if ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0010) != 0)
{
// Write the TxData to MSTXDATA Register, 1st 4bytes
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = *TxDataTableAdd++;
// Write the TxData to MSTXDATA Register, 2nd 4bytes
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = *TxDataTableAdd++;
}
// else Read 8bytes RxData from RxRegister
else
{
// Read the RxData, 1st 4bytes
*RxDataTableAdd++ = REGU32(MS_RX_DATA_REG_SUPERVISOR_ADDR);
// Read the RxData, 2nd 4bytes
*RxDataTableAdd++ = REGU32(MS_RX_DATA_REG_SUPERVISOR_ADDR);
}
}
// Check if RDY INT is asserted
if ((REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) & 0x0080) == 0x0080)
{
// Clear RDY INT
REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) |= 0x0080;
}
}
//---------------------------------------------------------------------------
// MS_TxRxTestDMAStart
//---------------------------------------------------------------------------
// This function does 16 bytes(32bit*4) loop test using DMA. For Tx, the
// first 8 bytes are already written into FIFO by CPU, thus DMA handles
// only 2 32 bit width element. For Rx, DMA is fully responsible to handle
// all 4 32 bit width element.
// Tx:
// TxDatatable in SDRAM -> MSTXFIFO
// Rx:
// MSRXFIFO -> RxDataTable in SDRAM
//
// Note that 16 bytes plus 2 CRC bytes!!
//---------------------------------------------------------------------------
void MS_TxRxTestDMAStart(void)
{
UWORD16 i, num;
// Init pointers
DmaTxAdd = (UWORD32*)DBG_CS4_SDRAM_1_ADDRESS; // SDRAM
DmaRxAdd = (UWORD32*)(DBG_CS4_SDRAM_1_ADDRESS + 0x10); // SDRAM+0x10
// Init Tx data in SDRAM and rewind pointer
for(i=0; i<4; i++)
{
*DmaTxAdd++ = TxDataTable[i];
}
DmaTxAdd = (UWORD32*)DBG_CS4_SDRAM_1_ADDRESS; // SDRAM
// Module Reset
MS_MrstBitValueAtReset();
// Set the DMA req condition
// TxFIFO Thershold (4bytes) and RxFIFO thershold (4bytes)
REGU16(MS_FIFO_CTL_REG_SUPERVISOR_ADDR) |= 0x0022;
// Enable I/F and select MSByte first mode and DMA enable
REGU16(MS_CNTL_REG_SUPERVISOR_ADDR) |= 0x8030;
// Tx Protocol Part
// DMA transfer : SDRAM to RHEA
// Initialization of DMA Channel
// Port Configuration
DMAT_ConfigPort(DMA_CHANNEL_0, // Channel number
DMA_SDRAM, // Source Port
DBG_CS4_SDRAM_1_ADDRESS + 0x08, // Source Address
DMA_RHEA, // Destination Port
MS_TX_DATA_REG_SUPERVISOR_ADDR); // Destination Address
// Configure the interrupt
DMA_EnableIntFlags(DMA_CHANNEL_0, // Channel Number
DISABLE, // Timeout Interrupt Enable
DISABLE, // Drop Interrupt Enable
DISABLE, // Half Frame Interrupt Enable
DISABLE, // Frame Interrupt Enable
DISABLE, // Last Frame Interrupt Enable
DISABLE); // Block Interrupt Enable
// Configure DMA according to DMA_CONFIG_MS_TX_32_0
DMAT_InitWithPattern(DMA_CHANNEL_0, DMA_PATTERN_MS_0, DMA_CONFIG_MS_TX_32_0);
// Set the DMA's registers
SDMA_SetupChannel(DMA_CHANNEL_0);
// Enable the transfer
DMA_EnableChannel(DMA_CHANNEL_0);
// Write the FirstTxData to MSTXDATA Register, total 8bytes
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = TxDataTable[0];
REGU32(MS_TX_DATA_REG_SUPERVISOR_ADDR) = TxDataTable[1];
// Wait the BS's condition good
while ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0300) != 0x0000)
{
}
// Set the TPC command to write mode and
// and Set the Number of TxByte (16bytes)
REGU16(MS_CMD_REG_SUPERVISOR_ADDR) = 0xb010; // Start Tx
// Wait the BS's condition good
while ((REGU16(MS_STAT_REG_SUPERVISOR_ADDR) & 0x0300) != 0)
{
}
// Rx Protocol Part
// DMA transfer : RHEA to SDRAM
// Initialization of DMA Channel
// Port Configuration
DMAT_ConfigPort(DMA_CHANNEL_0, // Channel number
DMA_RHEA, // Source Port
MS_RX_DATA_REG_SUPERVISOR_ADDR, // Source Address
DMA_SDRAM, // Destination Port
DBG_CS4_SDRAM_1_ADDRESS + 0x10); // Dsetination Address
// Configure the interrupt
DMA_EnableIntFlags(DMA_CHANNEL_0, // Channel Number
DISABLE, // Timeout Interrupt Enable
DISABLE, // Drop Interrupt Enable
DISABLE, // Half Frame Interrupt Enable
DISABLE, // Frame Interrupt Enable
DISABLE, // Last Frame Interrupt Enable
ENABLE); // Block Interrupt Enable
// Configure DMA according to DMA_CONFIG_MS_RX_32_0
DMAT_InitWithPattern(DMA_CHANNEL_0, DMA_PATTERN_MS_0, DMA_CONFIG_MS_RX_32_0);
// Set the DMA's registers
SDMA_SetupChannel(DMA_CHANNEL_0);
// Enable the transfer
DMA_EnableChannel(DMA_CHANNEL_0);
// Set the TPC command to read mode and
// set the number of RxByte (16bytes)
REGU16(MS_CMD_REG_SUPERVISOR_ADDR) = 0x4010; // Start Rx
// Wait for end of Rx protocol and end of this test
while (1);
}
//---------------------------------------------------------------------------
// MS_TxRxDmaIsr
//---------------------------------------------------------------------------
// ISR for DMA based loop test. This is called at the end of Rx protocol
// by DMA_BLOCK_END INT and does comparison between Tx and Rx tables.
//---------------------------------------------------------------------------
BOOL MS_TxRxDmaIsr(void)
{
UWORD16 i;
BOOL ok = True;
// Compare Txed and Rxed data
for (i=0; i<4; i++)
{
ok &= (*DmaTxAdd++ == *DmaRxAdd++);
}
// Check CRC
ok &= ((REGU16(MS_I_DATA_REG_SUPERVISOR_ADDR) & 0x0002) == 0x0000);
return(ok);
}
//---------------------------------------------------------------------------
void MS_TestResetValue(void)
{
TEST_FIELD_RESET_VALUE32(MS_GCM_CLK_REG,MS_GCM_CLK_REG);
REG32(MS_GCM_CLK_REG)|=0x1; // Enable clock
TEST_FIELD_RESET_VALUE(MS_CMD_REG,MSCMD_TPC);
TEST_FIELD_RESET_VALUE(MS_CMD_REG,MSCMD_DATASIZE);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_BSSTAT);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_INT);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_DRQ);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_RXFREQ);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_TXFREQ);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_RBE);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_RBF);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_TBE);
TEST_FIELD_RESET_VALUE(MS_STAT_REG,MSSTAT_TBF);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_SWAP);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_MRST);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_TRRST);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_PWS);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_SIEN);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_DMAEN);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_NOCRC);
TEST_FIELD_RESET_VALUE(MS_CNTL_REG,MSCNTL_BSYCNT);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_RDY);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_SIF);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_DRQ);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_PIN1);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_PIN0);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_CRC);
TEST_FIELD_RESET_VALUE(MS_I_DATA_REG,MSIDATA_TOE);
TEST_FIELD_RESET_VALUE(MS_I_CTL_REG,MSICTL_INTEN);
TEST_FIELD_RESET_VALUE(MS_I_CTL_REG,MSICTL_DRQSL);
TEST_FIELD_RESET_VALUE(MS_I_CTL_REG,MSICTL_PINEN);
TEST_FIELD_RESET_VALUE(MS_PP_CTL_REG,MSPPCTL_GPIODIR1);
TEST_FIELD_RESET_VALUE(MS_PP_CTL_REG,MSPPCTL_GPIODIR0);
TEST_FIELD_RESET_VALUE(MS_FIFO_CTL_REG,MSFIFOCTL_TXTHRESH);
TEST_FIELD_RESET_VALUE(MS_FIFO_CTL_REG,MSFIFOCTL_RXTHRESH);
TEST_FIELD_RESET_VALUE(MS_FIFO_CNT_REG,MSFIFOCNT_TXCNT);
TEST_FIELD_RESET_VALUE(MS_FIFO_CNT_REG,MSFIFOCNT_RXCNT);
TEST_FIELD_RESET_VALUE32(MS_GCM_RESET_REG,MS_GCM_RESET_REG);
PRINT_CURRENT_ERROR_STATUS(MS_TEST_RESET_VALUE_SUCCEEDED);
}
void MS_TestRegistersAccess(void)
{
MODIFY_FIELD_RESET_VALUE32(MS_GCM_CLK_REG,MS_GCM_CLK_REG);
REG32(MS_GCM_CLK_REG)|=0x1; // Enable clock
MODIFY_FIELD_RESET_VALUE16(MS_CMD_REG,MSCMD_TPC);
MODIFY_FIELD_RESET_VALUE16(MS_CMD_REG,MSCMD_DATASIZE);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_SWAP);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_PWS);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_SIEN);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_DMAEN);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_NOCRC);
MODIFY_FIELD_RESET_VALUE16(MS_CNTL_REG,MSCNTL_BSYCNT);
MODIFY_FIELD_RESET_VALUE16(MS_I_CTL_REG,MSICTL_INTEN);
MODIFY_FIELD_RESET_VALUE16(MS_I_CTL_REG,MSICTL_DRQSL);
MODIFY_FIELD_RESET_VALUE16(MS_I_CTL_REG,MSICTL_PINEN);
MODIFY_FIELD_RESET_VALUE16(MS_PP_CTL_REG,MSPPCTL_GPIODIR1);
MODIFY_FIELD_RESET_VALUE16(MS_PP_CTL_REG,MSPPCTL_GPIODIR0);
MODIFY_FIELD_RESET_VALUE16(MS_FIFO_CTL_REG,MSFIFOCTL_TXTHRESH);
MODIFY_FIELD_RESET_VALUE16(MS_FIFO_CTL_REG,MSFIFOCTL_RXTHRESH);
MODIFY_FIELD_RESET_VALUE32(MS_GCM_RESET_REG,MS_GCM_RESET_REG);
PRINT_CURRENT_ERROR_STATUS(MS_TEST_REGISTER_ACCESS_SUCCEEDED);
}
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