spi100khz.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments (TI)
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work.
//   Created 2000, (C) Copyright 2000-2002 TI.  All rights reserved.
//
//   Filename             : spi100khz.c
//
//===============================================================================
#include "test.h"
#include "spi100khz.h"

// We always use 'module' as the parameter name for SPI module
#define  MOD__REG_PTR( regName)         SPI__REG_PTR(module,regName)

//---------------------------------------------------------------------
// NAME        : SPI_100khzTestRegisters
// DESCRIPTION : Test the reset values + accessibility
//               of SPI_100K_<module> registers.
// PARAMETERS  :
//      module => SPI module.
// RETURN VALUE: None.
// LIMITATIONS : To invoke on Reset only.
//---------------------------------------------------------------------
UWORD16 SPI_100khzTestRegisters (SPI_module_t module)
{
  UWORD16 val;
  UWORD16 result = TEST_OK;

  //RESET VALUE ON SET1 REGISTER
  val = *MOD__REG_PTR(SET1) & SPI_100KHZ_SET1_REG_MASK;
  if ( val != SPI_100KHZ_SET1_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_SET1_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON SET2 REGISTER
  val = *MOD__REG_PTR(SET2) & SPI_100KHZ_SET2_REG_MASK;
  if ( val != SPI_100KHZ_SET2_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_SET2_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON CTRL REGISTER
  val = *MOD__REG_PTR(CTRL) & SPI_100KHZ_CTRL_REG_MASK;
  if ( val != SPI_100KHZ_CTRL_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_CTRL_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON STATUS REGISTER
  //To read Status register the internal clock must be running
  SPI_100KHZ_StartClock();
  val = *MOD__REG_PTR(STATUS) & SPI_100KHZ_STATUS_REG_MASK;
  if ( val != SPI_100KHZ_STATUS_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_STATUS_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON TX_LSB REGISTER
  val = *MOD__REG_PTR(TX_LSB);
  if ( val != SPI_100KHZ_TX_LSB_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_TX_LSB_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON TX_MSB REGISTER
  val = *MOD__REG_PTR(TX_MSB);
  if ( val != SPI_100KHZ_TX_MSB_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_TX_MSB_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON RX_LSB REGISTER
  val = *MOD__REG_PTR(RX_LSB);
  if ( val != SPI_100KHZ_RX_LSB_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_RX_LSB_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //RESET VALUE ON RX_MSB REGISTER
  val = *MOD__REG_PTR(RX_MSB);
  if ( val != SPI_100KHZ_RX_MSB_REG_RESET_VALUE )
  {
      RES_Set(SPI_100KHZ_RX_MSB_REG_RESET_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //ACCESS TO SET1
  *MOD__REG_PTR(SET1) = 0x07;
  val = *MOD__REG_PTR(SET1)  & SPI_100KHZ_SET1_REG_MASK;
  if ( val != 0x07 )
  {
      RES_Set(SPI_100KHZ_SET1_REG_ACCESS_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //ACCESS TO SET2
  *MOD__REG_PTR(SET2) = 0x7FFF;
  val = *MOD__REG_PTR(SET2) & SPI_100KHZ_SET2_REG_MASK;
  if ( val != 0x7FFF )
  {
      RES_Set(SPI_100KHZ_SET2_REG_ACCESS_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //ACCESS TO CTRL
  *MOD__REG_PTR(CTRL) = 0x03FC;
  val = *MOD__REG_PTR(CTRL) & SPI_100KHZ_CTRL_REG_MASK;
  if ( val != 0x03FC )
  {
      RES_Set(SPI_100KHZ_CTRL_REG_ACCESS_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //ACCESS TO TX LSB
  *MOD__REG_PTR(TX_LSB)  = 0xFFFF;
  val = *MOD__REG_PTR(TX_LSB);
  if ( val != 0xFFFF )
  {
      RES_Set(SPI_100KHZ_TX_LSB_REG_ACCESS_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  //ACCESS TO TX MSB
  *MOD__REG_PTR(TX_MSB) = 0xFFFF;
  val = *MOD__REG_PTR(TX_MSB);
  if ( val != 0xFFFF )
  {
      RES_Set(SPI_100KHZ_TX_MSB_REG_ACCESS_ERROR);
      RES_Set(val);
      result = TEST_BAD;
  }
  else  RES_Set(TEST_OK);

  return result;
}

/*
-------------------------------------------------------------------------
        SPI_100khzInitSet1                                              -
-------------------------------------------------------------------------
*/
void SPI_100khzInitSet1 (SPI_module_t module,
                   SPI_100KHZ_EnableClock_t enClk,
                   SPI_100KHZ_Ptv_t         Pscale,
                   SPI_100KHZ_MaskIntWr_t   IntWr,
                   SPI_100KHZ_MaskIntRdWr_t IntRdWr)
{
  *MOD__REG_PTR(SET1) = (enClk
                  | Pscale  << SPI_100KHZ_SET1_PTV_POSBIT
                  | IntWr   << SPI_100KHZ_SET1_MSK0_POSBIT
                  | IntRdWr << SPI_100KHZ_SET1_MSK1_POSBIT);
}

/*
-------------------------------------------------------------------------
        SPI_100khzInitSet2                                              -
-------------------------------------------------------------------------
*/
void SPI_100khzInitSet2 (SPI_module_t module,
                   SPI_100KHZ_EdgeClock_t AcedgDevi,
                   SPI_100KHZ_Ptspen_t    Ptspen,
                   SPI_100KHZ_Ltspen_t    Ltspen)
{
  *MOD__REG_PTR(SET2) = (AcedgDevi
                   | Ptspen << SPI_100KHZ_SET2_P_POSBIT
                   | Ltspen << SPI_100KHZ_SET2_L_POSBIT );
}

/*
-------------------------------------------------------------------------
        SPI_100khzInitCTRL                                             -
-------------------------------------------------------------------------
*/
void SPI_100khzInitCTRL (SPI_module_t module,
                   SPI_100KHZ_CtrlRd_t      Rdproc,
                   SPI_100KHZ_CtrlWr_t      Wrproc,
                   SPI_100KHZ_TrxLength_t   Nbsize,
                   SPI_100KHZ_DeviceIndex_t DeviceNumber)
{
  *MOD__REG_PTR(CTRL) = (Rdproc
                  | Wrproc       << SPI_100KHZ_CTRL_WR_POSBIT
                  | Nbsize       << SPI_100KHZ_CTRL_NB_POSBIT
                  | DeviceNumber << SPI_100KHZ_CTRL_AD_POSBIT);
}

/*
-------------------------------------------------------------------------
        SPI_100khzReadStatus                                            -
-------------------------------------------------------------------------
*/
SPI_100KHZ_Status_t SPI_100khzReadStatus (SPI_module_t module)
{
  UWORD16 value = *MOD__REG_PTR(STATUS) & SPI_100KHZ_STATUS_REG_MASK;

  if (value == SPI_100KHZ_STATUS_BUSY_VALUE)
    return SPI_100KHZ_BUSY; //Neither READ_END nor WRITE_END reached
  else
    return SPI_100KHZ_FREE; //Either Received registers are loaded (READ_END)
                      //or the serialization write is finished (WRITE_END)
}

/*
-------------------------------------------------------------------------
        SPI_100khzIsReadEnd                                             -
-------------------------------------------------------------------------
*/
boolean_t SPI_100khzIsReadEnd (SPI_module_t module)
{
  if ( (*MOD__REG_PTR(STATUS) & SPI_100KHZ_STATUS_RE_MASK)
        == SPI_100KHZ_STATUS_RE_MASK )
       return True;
  else return False;
}

/*
-------------------------------------------------------------------------
        SPI_100khzIsWriteEnd                                            -
-------------------------------------------------------------------------
*/
boolean_t SPI_100khzIsWriteEnd (SPI_module_t module)
{
  if ( (*MOD__REG_PTR(STATUS) & SPI_100KHZ_STATUS_WE_MASK)
        == SPI_100KHZ_STATUS_WE_MASK )
       return True;
  else return False;
}

/*
-------------------------------------------------------------------------
        SPI_100khzWriteTxLsb                                            -
-------------------------------------------------------------------------
*/
void SPI_100khzWriteTxLsb (SPI_module_t module, UWORD16 Txlsb)
{
  *MOD__REG_PTR(TX_LSB) = Txlsb;
}

/*
-------------------------------------------------------------------------
        SPI_100khzWriteTxMsb                                            -
-------------------------------------------------------------------------
*/
void SPI_100khzWriteTxMsb (SPI_module_t module, UWORD16 Txmsb)
{
  *MOD__REG_PTR(TX_MSB) = Txmsb;
}

/*
-------------------------------------------------------------------------
        SPI_100hzReadRxLsb                                              -
-------------------------------------------------------------------------
*/
UWORD16 SPI_100hzReadRxLsb (SPI_module_t module)
{
  return *MOD__REG_PTR(RX_LSB);
}

/*
-------------------------------------------------------------------------
        SPI_100khzReadRxMsb                                             -
-------------------------------------------------------------------------
*/
UWORD16 SPI_100khzReadRxMsb(SPI_module_t module)
{
  return *MOD__REG_PTR(RX_MSB);
}

/*
-------------------------------------------------------------------------
        SPI_100khzStartClock                                            -
-------------------------------------------------------------------------
*/
void SPI_100khzStartClock (SPI_module_t module)
{
  SetBit (*MOD__REG_PTR(SET1), SPI_100KHZ_SET1_EN_CLK_MASK);
}

/*
-------------------------------------------------------------------------
        SPI_100khzStopClock                                             -
-------------------------------------------------------------------------
*/
void SPI_100khzStopClock (SPI_module_t module)
{
  ClearBit (*MOD__REG_PTR(SET1), SPI_100KHZ_SET1_EN_CLK_MASK);
}