📄 gdma_omap32.c
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ChptrA->TimeoutInt = GetGroupBits( Temp ,DMA_TOUT_POS ,DMA_TOUT_NUMB );
ChptrA->DropInt = GetGroupBits( Temp ,DMA_DROP_POS ,DMA_DROP_NUMB );
ChptrA->HalfFrameInt = GetGroupBits( Temp ,DMA_HALF_POS ,DMA_HALF_NUMB );
ChptrA->FrameInt = GetGroupBits( Temp ,DMA_FRAME_POS ,DMA_FRAME_NUMB );
ChptrA->LastFrameInt = GetGroupBits( Temp ,DMA_LASTFRAME_POS ,DMA_LASTFRAME_NUMB );
ChptrA->BlockInt = GetGroupBits( Temp ,DMA_BLOCK_POS ,DMA_BLOCK_NUMB );
}
else
{
LCD_CHANNEL_DESCRIPTOR_OMAP32* Chptr;
Chptr=&(SystemDma_omap32.LcdChannel);
//DMA_LCD_CTRL
//----------
Temp=LCD_DMA_ACC(GDMA_LCD_CTRL );
Chptr->Frame1ItCond = GetGroupBits( Temp ,DMA_LCD_FRAME1IT_POS ,DMA_LCD_FRAME1IT_NUMB );
Chptr->Frame2ItCond = GetGroupBits( Temp ,DMA_LCD_FRAME2IT_POS ,DMA_LCD_FRAME2IT_NUMB );
Chptr->BusErrorItCond = GetGroupBits( Temp ,DMA_LCD_BUSERRORIT_POS ,DMA_LCD_BUSERRORIT_NUMB );
// Clear the interrupt flags
SetGroupBits( Temp ,DMA_LCD_FRAME1IT_POS ,DMA_LCD_FRAME1IT_NUMB , DISABLE );
SetGroupBits( Temp ,DMA_LCD_FRAME2IT_POS ,DMA_LCD_FRAME2IT_NUMB , DISABLE );
SetGroupBits( Temp ,DMA_LCD_BUSERRORIT_POS ,DMA_LCD_BUSERRORIT_NUMB , DISABLE );
LCD_DMA_ACC(GDMA_LCD_CTRL )=Temp;
}
}
//-------------------------------------------------------------------------------
// NAME : DMAClearInterruptSource_OMAP32
//
// DESCRIPTION : Clear interrupt bits of the specified channel
//
// PARAMETERS : ChannelNumber DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32ClearInterruptSource(UWORD16 ChannelNumber) {
UWORD16 Temp;
Temp=DMA_ACC(NO_GLOB_REG, ChannelNumber ,DMA_CSR );
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32SetCdfi
//
// DESCRIPTION : Set the destination frame index
//
// PARAMETERS : ChannelNumb DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
// DMA_CHANNEL_LCD_OMAP32
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32SetCdfi(UWORD16 ChannelNumber, short int CDFI) {
if (ChannelNumber != DMA_CHANNEL_LCD_OMAP32)
{
CHANNEL_DESCRIPTOR_OMAP32* ChptrA;
ChptrA=&(SystemDma_omap32.DmaChannel[ChannelNumber]);
ChptrA->DFrameIndex = CDFI;
}
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32DisableChaining
//
// DESCRIPTION : Disable the chaining on specified channel
//
// PARAMETERS : ChannelNumber DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32DisableChaining(UWORD16 ChannelNumber)
{
UWORD16 Reg_val;
// SetGroupBits(DMA_ACC(NO_GLOB_REG,ChannelNumber,DMA_CLNK_CTRL),DMA_STOPLNK_POS,DMA_STOPLNK_NUMB,ENABLE);
Reg_val = DMA_ACC(NO_GLOB_REG,ChannelNumber,DMA_CLNK_CTRL);
Reg_val = ((Reg_val & 0x7fff) | 0x4000);
DMA_ACC(NO_GLOB_REG,ChannelNumber,DMA_CLNK_CTRL) = Reg_val;
}
//-------------------------------------------------------------------------------
// NAME : DMA_InitMemCore
//
// DESCRIPTION : Initialize the DMA memory cores
//
// PARAMETERS : UWORD16 value
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_InitMemCore(UWORD16 value) {
UWORD32 tmcr0_reg;
UWORD32 i;
//Set the GL_Memtest_tr bit in the TMCR0 register
tmcr0_reg = (*(UWORD32 *)(TMCR0_ADDR));
//Set the DMA Mem BIST bit
(*(UWORD32 *)(TMCR0_ADDR)) = (tmcr0_reg | 0x2000);
//Initialise all the GDMA memory cores
for (i=0; i < 16; i++) {
*((UWORD16 *)(MEM_RHEA_STROBE1_CS27_ADDR + (i << 6))) = value;
}
(*(UWORD32 *)(TMCR0_ADDR)) = tmcr0_reg;
}
//-------------------------------------------------------------------------------
// NAME : DMA_BistSet
//
// DESCRIPTION : Set the CPU BIST bit in the test register
//
// PARAMETERS : None
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_BistSet() {
UWORD32 tmcr0_reg;
//Set the GL_Memtest_tr bit in the TMCR0 register
tmcr0_reg = (*(UWORD32 *)(TMCR0_ADDR));
//Set the DMA Mem BIST bit
(*(UWORD32 *)(TMCR0_ADDR)) = (tmcr0_reg | 0x2000);
}
//-------------------------------------------------------------------------------
// NAME : DMA_BistReset
//
// DESCRIPTION : Reset the CPU BIST bit in the test register
//
// PARAMETERS : None
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_BistReset() {
UWORD32 tmcr0_reg;
//Set the GL_Memtest_tr bit in the TMCR0 register
tmcr0_reg = (*(UWORD32 *)(TMCR0_ADDR));
//Set the DMA Mem BIST bit
(*(UWORD32 *)(TMCR0_ADDR)) = (tmcr0_reg & ~(0x2000));
}
//-------------------------------------------------------------------------------
// NAME : DMA_BistMemsel
//
// DESCRIPTION : Select the memory block to test
//
// PARAMETERS : int memory block
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_BistMemsel(int mem_block) {
UWORD32 tmcr0_reg;
//Set the GL_Memtest_tr bit in the TMCR0 register
tmcr0_reg = (*(UWORD32 *)(TMCR0_ADDR));
//Set the DMA Mem BIST bit
(*(UWORD32 *)(TMCR0_ADDR)) = ((tmcr0_reg & ~(0xC000)) | ((mem_block & 0x3) << 14));
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32LcdChannelHandler
//
// DESCRIPTION : Interrupt service handler for the LCD Channel interrupts
//
// PARAMETERS : pointers to counters for each of the 3 interrupt conditions
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32LcdChannelHandler(UWORD8 *block1_end_counter, UWORD8 *block2_end_counter, UWORD8 *bus_error_counter, UWORD8 *unknown_counter) {
UWORD16 lcd_ctrl_reg;
lcd_ctrl_reg = LCD_DMA_ACC(GDMA_LCD_CTRL);
if (lcd_ctrl_reg & (1 << DMA_LCD_BUSERRORIT_POS)){
*bus_error_counter = (*bus_error_counter) + 1;
} else if (lcd_ctrl_reg & (1 << DMA_LCD_FRAME1IT_POS)) {
*block1_end_counter = (*block1_end_counter) + 1;
} else if (lcd_ctrl_reg & (1 << DMA_LCD_FRAME2IT_POS)) {
*block2_end_counter = (*block2_end_counter) + 1;
} else {
*unknown_counter = (*unknown_counter) + 1;
}
LCD_DMA_ACC(GDMA_LCD_CTRL) = lcd_ctrl_reg;
}
//-------------------------------------------------------------------------------
// NAME : LCDSharedhandler_OMAP32
//
// DESCRIPTION : Interrupt service handler for the LCD Controller interrupts
//
// PARAMETERS : pointers to counters for each of the 7 interrupt conditions
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32LcdSharedHandler(UWORD8 *lcd_done_counter, UWORD8 *lcd_vs_counter, UWORD8 *lcd_sync_counter, UWORD8 *lcd_acbias_counter, UWORD8 *lcd_lineint_counter, UWORD8 *lcd_fifounderflow_counter, UWORD8 *lcd_pl_counter, UWORD8 *unknown_counter) {
UWORD32 lcd_status_reg;
UWORD32 lcd_control_reg;
lcd_status_reg = REG32(LCD_STATUS_REG_SUPERVISOR_ADDR);
lcd_control_reg = REG32(LCD_CONTROL_REG_SUPERVISOR_ADDR);
lcd_control_reg &= 0x1fffffe;
if (lcd_status_reg & 1) {
*lcd_done_counter = (*lcd_done_counter) + 1;
} else if (lcd_status_reg & (1 << LCD32_VS_BIT_POSITION)){
*lcd_vs_counter = (*lcd_vs_counter) + 1;
REG32(LCD_CONTROL_REG_SUPERVISOR_ADDR) = lcd_control_reg;
} else if (lcd_status_reg & (1 << LCD_Sync_BIT_POSITION)) {
*lcd_sync_counter = (*lcd_sync_counter) + 1;
} else if (lcd_status_reg & (1 << LCD_ABC_BIT_POSITION)) {
*lcd_acbias_counter = (*lcd_acbias_counter) + 1;
} else if (lcd_status_reg & (1 << LCD32_LineInt_BIT_POSITION)) {
*lcd_lineint_counter = (*lcd_lineint_counter) + 1;
} else if (lcd_status_reg & (1 << LCD_FUF_BIT_POSITION)) {
*lcd_fifounderflow_counter = (*lcd_fifounderflow_counter) + 1;
} else if (lcd_status_reg & (1 << LCD_PL_BIT_POSITION)) {
*lcd_pl_counter = (*lcd_pl_counter) + 1;
REG32(LCD_CONTROL_REG_SUPERVISOR_ADDR) = lcd_control_reg;
} else {
*unknown_counter = (*unknown_counter) + 1;
}
REG32(LCD_STATUS_REG_SUPERVISOR_ADDR) = ~(lcd_status_reg);
}
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