gdma_omap32.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH7
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH7_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_8) : // Logical Channel 8
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH8_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH8_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH8
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH8_OMAP32);

      break;
    }

    case (DMA_CHANNEL_9) : // Logical Channel 9
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH9_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH9_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH9
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH9_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_10) : // Logical Channel 10
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH10_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH10_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH10
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH10_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_11) : // Logical Channel 11
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH11_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH11_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH11
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH11_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_12) : // Logical Channel 12
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH12_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH12_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH12
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH12_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_13) : // Logical Channel 13
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH13_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH13_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH13
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH13_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_14) : // Logical Channel 14
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH14_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH14_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH14
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH14_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_15) : // Logical Channel 15
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_CH15_OMAP32 ,        
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_CH15_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ CH15
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH15_OMAP32 );

      break;
    }

    case (DMA_CHANNEL_LCD_OMAP32) : // Logical Channel 15
    {
      INTH_InitLevel (INTH_FIQNIRQ_DMA_LCD_OMAP32, 
                      INTH_IRQ, // InterruptKind Irq or Fiq
                      INTH_FIQNIRQ_DMA_LCD_OMAP32 , // priority
                      INTH_LOW_LEVEL_SENSITIVE); // type level or edge
      // Enable IRQ LCD
      INTH_EnableOneIt(INTH_FIQNIRQ_DMA_LCD_OMAP32 );

      break;
    }

    default : 
    {
      break;
    }
  } // of switch

    // RES_StopVhdl();   
}

//-------------------------------------------------------------------------------
// NAME         : DMA_Omap32DisableInt 
//
// DESCRIPTION  : Disable the DMA interrupts after the transfer
//
// PARAMETERS  :     ChannelNumb      DMA_CHANNEL_0
//                                    DMA_CHANNEL_1
//                                    DMA_CHANNEL_2
//                                    DMA_CHANNEL_3
//                                    DMA_CHANNEL_4
//                                    DMA_CHANNEL_5
//                                    DMA_CHANNEL_6
//                                    DMA_CHANNEL_7
//                                    DMA_CHANNEL_8
//                                    DMA_CHANNEL_9
//                                    DMA_CHANNEL_10
//                                    DMA_CHANNEL_11
//                                    DMA_CHANNEL_12
//                                    DMA_CHANNEL_13
//                                    DMA_CHANNEL_14
//                                    DMA_CHANNEL_15
//                                    DMA_CHANNEL_LCD_OMAP32
//
// RETURN VALUE : None
//
//-------------------------------------------------------------------------------- 
void DMA_Omap32DisableInt(UWORD16 ChannelNumb) 
{
  // disable IRQ for the channel
  //---------------------------------
  switch (ChannelNumb)
  {
    case (DMA_CHANNEL_0) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH0);
      break;
    }
    case (DMA_CHANNEL_1) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH1);
      break;
    }
    case (DMA_CHANNEL_2) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH2);
      break;
    }
    case (DMA_CHANNEL_3) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH3);
      break;
    }
    case (DMA_CHANNEL_4) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH4);
      break;
    }
    case (DMA_CHANNEL_5) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH5);
      break;
    }
    case (DMA_CHANNEL_6) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH6_OMAP32);
      break;
    }
    case (DMA_CHANNEL_7) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH7_OMAP32);
      break;
    }
    case (DMA_CHANNEL_8) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH8_OMAP32);
      break;
    }
    case (DMA_CHANNEL_9) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH9_OMAP32);
      break;
    }
    case (DMA_CHANNEL_10) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH10_OMAP32);
      break;
    }
    case (DMA_CHANNEL_11) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH11_OMAP32);
      break;
    }
    case (DMA_CHANNEL_12) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH12_OMAP32);
      break;
    }
    case (DMA_CHANNEL_13) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH13_OMAP32);
      break;
    }
    case (DMA_CHANNEL_14) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH14_OMAP32);
      break;
    }
    case (DMA_CHANNEL_15) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_CH15_OMAP32);
      break;
    }
    case (DMA_CHANNEL_LCD_OMAP32) :
    {
      INTH_DisableOneIt(INTH_FIQNIRQ_DMA_LCD_OMAP32);
      break;
    }
    default : 
    {
      break;
    }
  }
}
//-------------------------------------------------------------------------------
// NAME         : DMA_Omap32GetCondBitsInterrupt       
//
// DESCRIPTION  : Get back the condition bits of the specified channel
//
// PARAMETERS   : ChannelNumber       DMA_CHANNEL_0   
//                                    DMA_CHANNEL_1   
//                                    DMA_CHANNEL_2   
//                                    DMA_CHANNEL_3   
//                                    DMA_CHANNEL_4   
//                                    DMA_CHANNEL_5   
//                                    DMA_CHANNEL_6   
//                                    DMA_CHANNEL_7   
//                                    DMA_CHANNEL_8   
//                                    DMA_CHANNEL_9   
//                                    DMA_CHANNEL_10  
//                                    DMA_CHANNEL_11  
//                                    DMA_CHANNEL_12  
//                                    DMA_CHANNEL_13  
//                                    DMA_CHANNEL_14  
//                                    DMA_CHANNEL_15  
//                                    DMA_CHANNEL_LCD_OMAP32
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32GetCondBitsInterrupt(UWORD16 ChannelNumber)
{
UWORD32 Temp;

  if (ChannelNumber != DMA_CHANNEL_LCD_OMAP32)
    {
    CHANNEL_DESCRIPTOR_OMAP32* ChptrA;
    ChptrA=&(SystemDma_omap32.DmaChannel[ChannelNumber]);
	//DMA_CSR
	//----------
    Temp=DMA_ACC(NO_GLOB_REG, ChannelNumber  ,DMA_CSR    );