📄 gdma_omap32.c
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Temp = LCD_DMA_ACC(GDMA_LCD_CCR);
Chptr->Priority = GetGroupBits(Temp,DMA_LCD_PRIORITY_POS,DMA_LCD_PRIORITY_NUMB);
Chptr->Enable = GetGroupBits(Temp,DMA_LCD_ENABLE_POS,DMA_LCD_ENABLE_NUMB);
Chptr->Autoinit = GetGroupBits(Temp,DMA_LCD_AUTOINIT_POS,DMA_LCD_AUTOINIT_NUMB);
Chptr->OMAP31Disable = GetGroupBits(Temp,DMA_LCD_COMPATIBLE_POS,DMA_LCD_COMPATIBLE_NUMB);
Chptr->Repeat = GetGroupBits(Temp,DMA_LCD_REPEAT_POS,DMA_LCD_REPEAT_NUMB);
Chptr->B1AddressMode = GetGroupBits(Temp,DMA_LCD_B1_AMODE_POS,DMA_LCD_B1_AMODE_NUMB);
Chptr->B2AddressMode = GetGroupBits(Temp,DMA_LCD_B1_AMODE_POS,DMA_LCD_B2_AMODE_NUMB);
//DMA_LCD_CTRL
//----------
Temp=LCD_DMA_ACC(DMA_LCD_CTRL );
Chptr->FrameMode = GetGroupBits( Temp ,DMA_LCD_FRAMEMODE_POS ,DMA_LCD_FRAMEMODE_NUMB );
Chptr->FrameItIe = GetGroupBits( Temp ,DMA_LCD_FRAMEIE_POS ,DMA_LCD_FRAMEIE_NUMB );
Chptr->BusErrorItIe = GetGroupBits( Temp ,DMA_LCD_BUSERROR_POS ,DMA_LCD_BUSERROR_NUMB );
Chptr->Frame1ItCond = GetGroupBits( Temp ,DMA_LCD_FRAME1IT_POS ,DMA_LCD_FRAME1IT_NUMB );
Chptr->Frame2ItCond = GetGroupBits( Temp ,DMA_LCD_FRAME2IT_POS ,DMA_LCD_FRAME2IT_NUMB );
Chptr->BusErrorItCond = GetGroupBits( Temp ,DMA_LCD_BUSERRORIT_POS ,DMA_LCD_BUSERRORIT_NUMB );
Chptr->LcdSrc = GetGroupBits( Temp ,DMA_LCD_SRC_POS ,DMA_LCD_SRC_NUMB );
Chptr->LcdDest = GetGroupBits( Temp ,DMA_LCD_DEST_POS ,DMA_LCD_DEST_NUMB );
//DMA_LCD_TOP_F1
//--------------
Chptr->LcdTopB1 = (GetGroupBits( LCD_DMA_ACC(DMA_LCD_TOP_F1_U) ,DMA_LCD_TOP_F1_U_POS ,DMA_LCD_TOP_F1_U_NUMB )<<16) |
(GetGroupBits( LCD_DMA_ACC(DMA_LCD_TOP_F1_L ) ,DMA_LCD_TOP_F1_L_POS ,DMA_LCD_TOP_F1_L_NUMB ));
//DMA_LCD_BOT_B1
//--------------
Chptr->LcdBotB1 = (GetGroupBits( LCD_DMA_ACC(DMA_LCD_BOT_F1_U ) ,DMA_LCD_BOT_F1_U_POS ,DMA_LCD_BOT_F1_U_NUMB )<<16) |
(GetGroupBits( LCD_DMA_ACC(DMA_LCD_BOT_F1_L ) ,DMA_LCD_BOT_F1_L_POS ,DMA_LCD_BOT_F1_L_NUMB ));
//DMA_LCD_TOP_B2
//--------------
Chptr->LcdTopB2 = (GetGroupBits( LCD_DMA_ACC(DMA_LCD_TOP_F2_U ) ,DMA_LCD_TOP_F2_U_POS ,DMA_LCD_TOP_F2_U_NUMB )<<16) |
(GetGroupBits( LCD_DMA_ACC(DMA_LCD_TOP_F2_L ) ,DMA_LCD_TOP_F2_L_POS ,DMA_LCD_TOP_F2_L_NUMB ));
//DMA_LCD_BOT_B2
//--------------
Chptr->LcdBotB2 = (GetGroupBits( LCD_DMA_ACC(DMA_LCD_BOT_F2_U ) ,DMA_LCD_BOT_F2_U_POS ,DMA_LCD_BOT_F2_U_NUMB )<<16) |
(GetGroupBits( LCD_DMA_ACC(DMA_LCD_BOT_F2_L ) ,DMA_LCD_BOT_F2_L_POS ,DMA_LCD_BOT_F2_L_NUMB ));
//DMA_LCD_SRC_EI_B1
//-----------------
Chptr->LcdSrcEI_B1 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_EI_B1),DMA_LCD_SRC_EI_B1_POS,DMA_LCD_SRC_EI_B1_NUMB);
//DMA_LCD_SRC_EI_B2
//-----------------
Chptr->LcdSrcEI_B1 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_EI_B2),DMA_LCD_SRC_EI_B2_POS,DMA_LCD_SRC_EI_B2_NUMB);
//DMA_LCD_SRC_FI_B1
//-----------------
Chptr->LcdSrcFI_B1 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_FI_B1),DMA_LCD_SRC_FI_B1_POS,DMA_LCD_SRC_FI_B1_NUMB);
//DMA_LCD_SRC_FI_B2
//-----------------
Chptr->LcdSrcFI_B2 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_FI_B2),DMA_LCD_SRC_FI_B2_POS,DMA_LCD_SRC_FI_B2_NUMB);
//DMA_LCD_SRC_EN_B1
//-----------------
Chptr->LcdSrcEN_B1 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_EN_B1),DMA_LCD_SRC_EN_B1_POS,DMA_LCD_SRC_EN_B1_NUMB);
//DMA_LCD_SRC_EN_B2
//-----------------
Chptr->LcdSrcEN_B2 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_EN_B2),DMA_LCD_SRC_EN_B2_POS,DMA_LCD_SRC_EN_B2_NUMB);
//DMA_LCD_SRC_FN_B1
//-----------------
Chptr->LcdSrcFN_B1 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_FN_B1),DMA_LCD_SRC_FN_B1_POS,DMA_LCD_SRC_FN_B1_NUMB);
//DMA_LCD_SRC_FN_B2
//-----------------
Chptr->LcdSrcFN_B2 = GetGroupBits(LCD_DMA_ACC(GDMA_LCD_SRC_FN_B2),DMA_LCD_SRC_FN_B2_POS,DMA_LCD_SRC_FN_B2_NUMB);
}
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32EnableIntFlags
//
// DESCRIPTION : Setup interrupt flags in the channel structure specified
//
// PARAMETERS : ChannelNumber DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
//
//
//
// PARAMETERS : TimeoutIntEnable ENABLE or DISABLE
// DropIntEnable "
// HalfFrameIntEnable "
// FrameIntEnable "
// LastFrameIntEnable "
// BlockIntEnable "
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
void DMA_Omap32EnableIntFlags(
UWORD16 ChannelNumber,
UWORD32 TimeoutIntEnable,
UWORD32 DropIntEnable,
UWORD32 HalfFrameIntEnable,
UWORD32 FrameIntEnable,
UWORD32 LastFrameIntEnable,
UWORD32 BlockIntEnable)
{
CHANNEL_DESCRIPTOR_OMAP32* Chptr;
Chptr=&(SystemDma_omap32.DmaChannel[ChannelNumber]);
//DMA Interrupt Flag Control
//---------------------------
Chptr->TimeoutIntEnable = TimeoutIntEnable;
Chptr->DropIntEnable = DropIntEnable;
Chptr->HalfFrameIntEnable = HalfFrameIntEnable;
Chptr->FrameIntEnable = FrameIntEnable;
Chptr->LastFrameIntEnable = LastFrameIntEnable;
Chptr->BlockIntEnable = BlockIntEnable;
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32EnableLcdIntFlags
//
// DESCRIPTION : Setup interrupt flags in the channel structure specified
//
// PARAMETERS : FrameItIe ENABLE or DISABLE
// BusErrorItIe "
// FrameItIe ENABLE or DISABLE
// BusErrorItIe "
//
// RETURN VALUE : IS_OK or NOT_OK if something fail
//
//--------------------------------------------------------------------------------
void DMA_Omap32EnableLcdIntFlags(
UWORD32 FrameItIe,
UWORD32 BusErrorItIe)
{
LCD_CHANNEL_DESCRIPTOR_OMAP32* Chptr;
Chptr=&(SystemDma_omap32.LcdChannel);
//LCD Channel Interrupt Flag Control
//---------------------------
Chptr->FrameItIe = FrameItIe;
Chptr->BusErrorItIe = BusErrorItIe;
}
//-------------------------------------------------------------------------------
// NAME : DMA_Omap32ConfigInt
//
// DESCRIPTION : Configure the DMA interrupts prior to transfer
//
// PARAMETERS : ChannelNumb DMA_CHANNEL_0
// DMA_CHANNEL_1
// DMA_CHANNEL_2
// DMA_CHANNEL_3
// DMA_CHANNEL_4
// DMA_CHANNEL_5
// DMA_CHANNEL_6
// DMA_CHANNEL_7
// DMA_CHANNEL_8
// DMA_CHANNEL_9
// DMA_CHANNEL_10
// DMA_CHANNEL_11
// DMA_CHANNEL_12
// DMA_CHANNEL_13
// DMA_CHANNEL_14
// DMA_CHANNEL_15
// DMA_CHANNEL_LCD_OMAP32
//
// RETURN VALUE : None
//
//--------------------------------------------------------------------------------
void DMA_Omap32ConfigInt(UWORD16 ChannelNumb)
{
//-----------------------------------------------------
// Initialize ARM Interrupt Handler
//-----------------------------------------------------
switch(ChannelNumb)
{
case (DMA_CHANNEL_0) : //Logical Channel 0
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH0,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH0, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH0
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH0);
break;
}
case (DMA_CHANNEL_1) : // Logical Channel 1
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH1,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH1, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH1
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH1);
break;
}
case (DMA_CHANNEL_2) : // Logical Channel 2
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH2,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH2, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH2
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH2);
break;
}
case (DMA_CHANNEL_3) : // Logical Channel 3
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH3,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH3, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH3
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH3);
break;
}
case (DMA_CHANNEL_4) : // Logical Channel 4
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH4,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH4, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH4
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH4);
break;
}
case (DMA_CHANNEL_5) : // Logical Channel 5
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH5,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH5, // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH5
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH5);
break;
}
case (DMA_CHANNEL_6) : // Logical Channel 6
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH6_OMAP32 ,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH6_OMAP32 , // priority
INTH_LOW_LEVEL_SENSITIVE); // type level or edge
// Enable IRQ CH6
INTH_EnableOneIt(INTH_FIQNIRQ_DMA_CH6_OMAP32);
break;
}
case (DMA_CHANNEL_7) : // Logical Channel 7
{
INTH_InitLevel (INTH_FIQNIRQ_DMA_CH7_OMAP32 ,
INTH_IRQ, // InterruptKind Irq or Fiq
INTH_FIQNIRQ_DMA_CH7_OMAP32 , // priority
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