juno_comm.asm

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Copyright 1999, 2000 by Texas Instruments Incorporated. All rights reserved.
;; Property of Texas Instruments Incorporated. Restricted rights to use,
;; duplicate or disclose this code are granted through contract.
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; $Workfile: juno_comm.asm
;; $Modtime: 9/15/00 6:34p $
;; $Author: Marcus-Alan Gilbert
;; $Revision: 3 $
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; $Description: $
;;
;; Contains functions for communications via the Serial Peripheral Interface
;; of the PerseusDC motherboard FPGA and the Juno Device
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; For a desription of the timing parameters usd in this section please see page
;; 7-7 of the USAR Juno Technical Reference (DOC8-007-001-TR-072) 
;; May need the INIT_RESP section in the Data area to prevent it from being treated
;; as code and possibly being placed in Flash instead of SDRAM.  

        .data
INIT_RESP    .byte 0,0,0,0
quot_remainder .word 0,0
        .text
        .include juno_comm.inc
        .ref U$DIV
        .def $init_juno
        .def $packet_write
        .def $packet_read
        .def $wait
        .def _pause
        
INIT_PACKET  .byte SIMP_HDR, INIT_CMD, LRC_INIT, 0 ; Extra Byte Pattern to word align data




$init_juno
  ; int _init_juno(int *, int *, int) 
  ; Parameters r0 - pointer to int array representing the FPGA registers, 
  ; r1 - pointer to an int array representing the Timer Registers, 
  ; r2 - frequency of chip.
  ; locals 
  ; r3 HID Register Pointer/Periph Reset Register pointer
  ; r4 HID Register Value/Periph Reset Register contents
  ; r5 pointer to HID response
  ; r6 HID Response, r7 pointer to HID test valueD
  ; Returns 1 if unsigned char fails, zero other wise.  
  ; Save SOE (Save on Entry) Registers 
  
  push       {r4,r5,r6,r7,lr}

; Set Peripheral Register Reset 
  add       r3, r0, #PERIPH_RESET
  ldrb      r4, [r3]
  mov       r5, #HID_ACTIVE
  orr       r4, r5 
  strb      r4, [r3]

; Set MOSI and CLK High to indicate an SPI (synchronous type transfer)
  mov       r3, #HID_OFFSET
  add       r3, r3, r0 
  mov       r4, #MOSI_CLK_HI
  strb      r4, [r3]

; Take HID out of Reset and Indicate that HOST is active
    
  mov       r4, #(HID_HOST_ACTIVE | MOSI_CLK_HI) ; Take HID out of RESET 
  strb      r4, [r3]    

; Wait for ATN to go inactive coming out of Reset (after cold boot ~4.3 ms)

  mov       r5, #ATN_ACTIVE
  ldr       r4, [r3]
  tst       r4, r5
  beq       $-4        ; Re-evaluate (branch to two instruction before)

; Pause for Tmnext,  i.e. ATN Release to SS re-assertion = 120 microseconds.
  pausem16  r2, Tmnext, r1 
   
; Call Functions for Writing and Reading Registers 

  packet_writem16 INIT_PACKET, 3, r0, r1, r2 ; Packet length 3, 65MHz
  packet_readm16  resp_ptr, r0, r1, r2

; Verify Response 
  adr   r5, resp_ptr
  ldr   r5, [r5]
  ldr   r6, [r5]
  adr   r7, VERIFY_PAT ; Verify Pattern is the Initialization Complete Packet
  ldr   r3, [r7]
  eor   r3, r6 
  mov   r0, #0      ; Pass Condition 
  beq   DONE
  add   r6, r6, #0   ; Test for all zeroes in 
  mov   r0, #1      ; Fail Condition
  beq   DONE
  mov   r0, r6      ; move R6 into R0
  
DONE 
; Restore SOE registers 
  pop       {r4,r5,r6,r7,pc}

VERIFY_PAT   .byte SIMP_HDR, INIT_CMPLT, LRC_CMPLT, 0;
        
$packet_write 
  ; void packet_write(BYTE [],  BYTE, int *, int *, int) 
  ; Parameters r0 - pointer to BYTE array, r1 - # number of bytes,
  ; r2 - FPGA Pointer, r3 - Pointer to Timer, sp-4 (fifth argument) frequency of chip,
  ; locals r4 byte to send, r5 bit counter, r6 byte counter, 
  ; r7 MOSI (Master Out Slave In) bit, r8 HID Register Value, r9 HID Register 
  ; Pointer, r10 = 1, r11 copy of the current frequency of chip (in MHz)

  bx      pc                    ; At Run-Time To Change to 32 bits (ARM mode)
                                ; for swap
  nop                           ; No Operation
  .state32      ; 32 bits mode assembler directive (Link Time)

  ; Save SOE (Save on Entry) Registers 
 
  stmdb      sp!, {r4,r5,r6,r7,r8,r9,r10,r11,lr}
  ; Get Clock Freq off the stack 
  ldr        r11, [sp, #36]
        
  add        r9, r2, #HID_OFFSET
  ldrb       r8, [r9]

  ; Set Serial Clock HIGH, MOSI High & Assert #SS
  orr        r8, r8, #(SS_ACTIVE | MOSI_CLK_HI)
  strb       r8, [r9]

  ; Check ATN, if equal to one then continue, could be up to 5 ms wait (Tmsa)
  ldr       r8, [r9]
  tst       r8, #ATN_ACTIVE
  ; beq     $-(2*4) 
  ; ****PERSEUS MOTHER MOD  START *****
  bne       $-(2*4)        
  ; ****PERSEUS MOTHER MOD  END *****
  ; Tmac _ATN to first clock pulse 
  ; Pause for a minimum of  100 usec
  pausem   r11, Tmac, r3
  ; Put the Sequence in MOSI MSB -> LSB 
  
  mov       r5, #7     ; Set Bit Counter 
  mov       r6, r1     
  mov       r10, #1    ; r8 will be the constant 1
 
SEND_BYTE 
    ldrb  r4, [r0]
SEND_BIT 
    and   r7, r10, r4, lsr r5
        mov   r7, r7, lsl #1 

    ; CLOCK LOW 
    and   r8, r8, #CLK_LOW_MOSI_LOW     
    orr   r8, r7, r8 
        strb  r8, [r9]
        ; Pause for the 2 usec Tslow time  
        pausem  r11, Tslow, r3
    ; CLOCK HIGH
        orr   r8, r8, #CLK_HIGH
        strb  r8, [r9]
        ; Pause for the 2 usec to complete Tsck time period 
        pausem  r11, Tslow, r3
        teq   r5, #0 
        sub   r5, r5, #0x1     ; Next Bit 
        bne   SEND_BIT    

        mov    r5, #7     ; reset Bit Counter 
    sub    r6, r6, #1     
        teq    r6, #0
        add    r0, r0, #1 
        beq    SS_HIGH

        ; Pause for the 150 usec inter byte spacing
        pausem r11, Tmib, r3
        b      SEND_BYTE

SS_HIGH
  ; de-assert #SS as soon as possible after last clock pulse 

        and     r8, r8, #SS_INACTIVE
    strb    r8, [r9]
  ; Wait for ATN to go inactive 
        ldr       r8, [r9]
        tst       r8, #ATN_ACTIVE
        ; bne       $-(2*4)
  ; ****PERSEUS MOTHER MOD  START *****
    beq       $-(2*4)
  ; ****PERSEUS MOTHER MOD  END *****
  ; Restore SOE registers 
   ldmia      sp!, {r4,r5,r6,r7,r8,r9,r10,r11,lr}
    
    add     r3, pc, #1      ; R3=PC+1 back to Thumb mode  16 bits mode
    bx      r3
        .state16

  ; Return 
    bx     lr
      

        .align 4
$packet_read 
; int packet_read(BYTE [], int *,  int *,  int) 
; Parameter r0 is pointer to output buffer, r1 - FPGA Pointer, r2 - Pointer to Timer, 
; r3 frequency of chip 
; Locals r4 bit counter, r5 shift amount, r6 instantaneous bit value of MISO,
;        r7 Hid Value, r8 Hid Pointer, r9 reconstructed byte, r10 byte count

; Save SOE (Save on Entry) Registers 
 bx      pc                     ; At Run-Time To Change to 32 bits (ARM mode)
                                ; for swap
  nop                           ; No Operation
  .state32      ; 32 bits mode assembler directive (Link Time)
 
    stmdb      sp!, {r4,r5,r6,r7,r8,r9,r10,lr}
    mov    r10,#1   
    mov    r9, #0

; Wait for ATN to go active  
        add        r8, r1, #HID_OFFSET 

        ldr       r7, [r8]
        tst       r7, #ATN_ACTIVE 
    ; beq       $-(2*4)