📄 intvecs_led.asm
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ClearFIQBit:
MOV r5, #FIQ_MASK
MOV r6, #CLEAR_BIT
B SetClearFIQIRQ
SetClearFIQIRQ:
MRS r7, SPSR ; read saved PSR
BIC r7, r7, r5 ; clear FIQ or IRQ bit of saved PSR
CMP r6, #CLEAR_BIT ; if equal to #CLEAR_BIT
BEQ STORE_SPSR ; do not set any bit of saved PSR
ORR r7, r7, r5 ; set FIQ or IRQ bit of saved PSR
STORE_SPSR:
MSR SPSR, r7 ; store saved PSR to set or clear FIQ or IRQ bit
B ExitSwi
DoIt:
;Set FIQ or IRQ mode before reset I/F bit to prevent interruption
MRS r4, CPSR ; read current PSR
BIC r4,r4,#MODE_MASK ; remove all mode bits
ORR r4,r4,r5 ; set desired mode
MSR CPSR, r4 ; set current mode to disable FIQ or IRQ catch
;STACK MANIPULATION
MOV SP, r0 ; stack address
MOV r1,r1,lsl #2 ; convertion from word size to byte size
ADD SP, r1, SP ; add size to get initial SP
BIC r4,r4,#MODE_MASK ; remove all mode bits
ORR r4,r4,#SUP_MODE
MSR CPSR, r4 ; reset supervisor mode
MRS r4,SPSR ; read stored status reg
BIC r4,r4,r6 ; Enable exception
MSR SPSR,r4 ; set stored status reg
ExitSwi:
MOVS PC, R14 ; return from SWI
.state16
$INT_SetSupervisor
MOV r3, LR
SWI #0xFA ; 0xFA : Enable INT_Swi
MOV PC, r3
$INT_SetUser:
MOV r3, LR
SWI #0xFB ; 0xFB : Enable INT_Swi
MOV PC, r3
;
; INT_EnableIRQ(unsigned stack, unsigned stackSize)
; R0 R1
;
; Enable IRQ and set up a stack - perform SWI to switch to supervisor mode
;
$INT_EnableIRQ:
MOV r3, LR
SWI #0xFD ; 0xFD : Enable IRQ
MOV PC, r3
;
; INT_EnableFIQ(unsigned stack, unsigned stackSize)
; R0 R1
;
; Enable FIQ and set up a stack - perform SWI to switch to supervisor mode
;
$INT_EnableFIQ:
MOV r3, LR
SWI #0xFC ; 0xFE : Enable FIQ
MOV PC, r3
;
; INT_Set_SVC_Stack(unsigned stack, unsigned stackSize)
; R0 R1
;
; Set up a stack for supervisor mode - perform SWI to switch to supervisor mode
;
$INT_Set_SVC_Stack:
MOV r3, LR
SWI #0xF5 ; 0xF5 : Set Supervisor Stack
MOV PC, r3
;
; INT_Set_SVC_Stack(unsigned stack, unsigned stackSize)
; R0 R1
;
; Set up a stack for supervisor mode - perform SWI to switch to supervisor mode
;
$INT_Set_AbortD_Stack:
MOV r3, LR
SWI #0xF4 ; 0xF4 : Set AbortD Stack
MOV PC, r3
;
; INT_SetIRQBit
;
; Set IRQ bit of PSR (Program Status Register)
; (Disable IRQ)
;
$INT_SetIRQBit:
MOV r3, LR
SWI #0xF0 ; 0xF0 : Set IRQ Bit of PSR
MOV PC, r3
;
; INT_ClearIRQBit
;
; Clear IRQ bit of PSR (Program Status Register)
; (Enable IRQ)
;
$INT_ClearIRQBit:
MOV r3, LR
SWI #0xF1 ; 0xF1 : Clear IRQ Bit of PSR
MOV PC, r3
;
; INT_SetFIQBit
;
; Set FIQ bit of PSR (Program Status Register)
; (Disable FIQ)
;
$INT_SetFIQBit:
MOV r3, LR
SWI #0xF2 ; 0xF2 : Set FIQ Bit of PSR
MOV PC, r3
;
; INT_ClearFIQBit
;
; Clear FIQ bit of PSR (Program Status Register)
; (Enable FIQ)
;
$INT_ClearFIQBit:
MOV r3, LR
SWI #0xF3 ; 0xF3 : Clear FIQ Bit of PSR
MOV PC, r3
;; ===========================================================================================
;; ==DO NOT REMOVE=======USE FOR TDL GENERATION=============================================================================
;; ===========================================================================================
.sect ".exitsim"
.state32
.half 0x0000 ; will be arm9 code size -- 1
.half 0x0000 ; will be arm9 code size -- 2
.half 0x0000 ; will be lead3 code size -- 3
.half 0x0000 ; will be lead3 code size -- 4
.half 0x01a2 ; value to put in the dpll -- 5
.half 0xF0F0 ; free var -- 6
.half 0x5A5A ; free var -- 7
.half 0xF0F0 ; free var -- 8
.half 0x5A5A ; free var -- 9
.half 0xF0F0 ; free var -- 10
.half 0x5A5A ; free var -- 11
.half 0xF0F0 ; free var -- 12
.half 0x5A5A ; free var -- 13
.half 0xF0F0 ; free var -- 14
.half 0x5A5A ; free var -- 15
.half 0xF0F0 ; free var -- 16
.half 0x5A5A ; free var -- 17
.half 0xF0F0 ; free var -- 18
.half 0x5A5A ; free var -- 19
.half 0xF0F0 ; free var -- 20
.half 0x5A5A ; free var -- 21
.half 0xF0F0 ; free var -- 22
.half 0x5A5A ; free var -- 23
.half 0xF0F0 ; free var -- 24
.half 0x5A5A ; free var -- 25
.half 0xF0F0 ; free var -- 26
.half 0x5A5A ; free var -- 27
.half 0xF0F0 ; free var -- 28
.half 0x5A5A ; free var -- 29
.half 0xF0F0 ; free var -- 30
.half 0x5A5A ; free var -- 31
.half 0xF0F0 ; free var -- 32
;; ===========================================================================================
;; ==DO NOT REMOVE=======USE FOR TDL GENERATION=============================================================================
;; ===========================================================================================
.state32
DUMP_SPY:
LDR R2,SPY_SPACE ;; Pointer to spy result mem location is in R2
LDR R0,[R2] ;; R0 contains pointer to first spy result
LDR R1,SPY_OUTPUT ;; R1 contains pointer to spy component
;; Stores error count in R4
LDRH R4, [R0, #4] ;; (spy pointer+2 as first outputs are 5555, AAAA)
;; Set the global result of the test
;; on EXEC_PIN (= gpio(2))
;; 1 if OK
;; 0 if fail
;; -------------------------------
LDR R6,END_GPIO_OUT ;; R6 contains pointer on GPIO out space
LDR R5,[R6] ;; Loads GPIO out reg to R5
BIC R5, R5, #0x4 ;; Sets R5 bit 2 to zero
CMP R4, #0 ;; If R4 == 0 (no error)
ORREQ R5, R5, #0x4 ;; Sets R5 bit 2 to one
;;------------------------
;;Now R5 contains the value to be loaded at the address pointed by R6
;; Loops until spy last address is reached
LDR R3, SPY_END ;; R3 contains F1F1 (last spy value)
LDRH R2, [R0], #2 ;; R2 contains first (0x5555) spy value, R0 points to 2nd spy value
DUMP_LOOP:
STRH R2, [R1], #2 ;; Puts R2 content into address pointed by R1, R1 is incremented
LDRH R2, [R0], #2 ;; Stores into R2 address pointer by R0, R0 is incremented
CMP R2, R3 ;; If R2 != F1F1
BNE DUMP_LOOP ;; Loops
END_SIMU:
;; Writes 0xFFFF to spy (end simulation)
LDR R0,SPY_ENDSPACE
LDR R1,SPY_STOP
STR R5,[R6] ;; Sets GPIO_2 to its correct value
STRH R1,[R0] ;; Actually writes 0xFFFF
WAIT:
B WAIT
SPY_ACED .word 0xACED ;
SPY_DEAD .word 0xDEAD ;
RESULT_OK .word 0x0000 ;
END_GPIO_CNTL .word 0xFFFCE008 ;
END_GPIO_OUT .word 0xFFFCE004 ;
EXEC_PIN .word 0x4 ; pin index 2
HEADER_5555 .word 0x5555
SPY_END .word 0xF1F1
SPY_STOP .word 0xFFFF
SPY_SPACE .word 0x20003FFC
SPY_OUTPUT .word 0x05000000
SPY_ENDSPACE .word 0x050000FE
.state16
$DisableCache_prefetch
ADR R7, Mode_32_Bits
BX R7
.state32
Mode_32_Bits
;ARM_TEST_AND_CLEAN_DCACHE
clean_loop
mrc p15, #0, R15, c7, c14, #3
bne clean_loop
; ARM_DRAIN_WRITE_BUFFER
mov r0, #0
mcr p15, #0, r0, c7, c10, #4
;ARM_DCACHE_OFF
mrc p15, #0, r0, c1, c0
mov r1, #0x4
bic r0, r0, r1
mcr p15, #0, r0, c1, c0
;ARM_FLUSH_ICACHE
mov r0, #0
mcr p15, #0, r0, c7, c5
;ARM_ICACHE_OFF;
mrc p15, #0, r0, c1, c0
mov r1, #0x1000
bic r0, r0, r1
mcr p15, #0, r0, c1, c0
;ARM_DISABLE_PREFETCH
mrc p15, #0, r0, c15, c0
mov r1, #0x10000
bic r0, r0, r1
mcr p15, #0, r0, c15, c0
ADR R7, Mode_16_Bits+1
BX R7
.state16
Mode_16_Bits
mov pc, lr
.end ; Terminate assembly
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