📄 intvecs_led.asm
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LDR R1,ARM_CKCTL_val
STR R1,[R0]
;
; Get the constants
; and set the dpll with the value read
;
LDR R0, AddrDpll ;; R0 contains DPLL control register address
LDR R2, ValueDpll ;; R2 contains DPLL control value
STRH R2, [R0] ;; Store DPLL control value in DPLL control register;;;
RUN_PROG2:
; Disable ARM GPIO Clock
LDR R1,ARM_GPIO_CLK_POS ; load ARM GPIO Clock bit position
LDR R2,addrClkrst_IDLECT2 ; load ARM CLKM IDLECT2 register address
LDR R3, [R2] ; Get back the value of the ARM CLKM IDLECT2 register
BIC R3,R3,R1 ; Clear the ARM GPIO Clock enable bit
STR R3,[R2] ; Write the ARM CLKM IDLECT2 register
; Initialize ARM925T internal registers.
MOV R0, #0
MOV R1, #0
MOV R2, #0
MOV R3, #0
MOV R4, #0
MOV R5, #0
MOV R6, #0
MOV R7, #0
MOV R8, #0
MOV R9, #0
MOV R10, #0
MOV R11, #0
MOV R12, #0
B _c_int00 ; RESET INTERRUPT
;; ===========================================================================================
;; ===========================================================================================
;; ===========================================================================================
GPIO_CNTL .word 0xFFFCE008 ;
GPIO_OUT .word 0xFFFCE004 ;
GPIO_PIN .word 0x4 ; pin index 2
AddrConstant .word 0x20003F00 ;
AddrDpllLed .word 0x20003F08 ;
MarkerEndSection .word 0xF0F05A5A ;
AddrSourceProgram .word 0x0 ;
AddrDestProgram .word 0x20020000 ;
AddrSourceExitRoutine .word 0x4000 ;
AddrDestExitRoutine .word 0x20024000 ;
EndProgSpace .word 0x4200 ;
AddrPassDetector .word 0x20007FFC ;
FirstPass .word 0xAAAA
OffsetLargePageSubsection .word 0x1000 ;
CS0_ADD .word 0x00000000 ;
CS1_ADD .word 0x05000000 ;
CS2_ADD .word 0x08000000 ;
CS3_ADD .word 0x0C000000 ;
CS4_ADD .word 0x10000000 ;
CS6_ADD .word 0x20000000 ;
CS6_MMUTAB_ADD .word 0x20010000 ;
RHEA_ADD .word 0xFFFE0000 ;
TTB .word 0x20010000 ;
TTB_1ST_CS0 .word 0x20010400 ;
TTB_1ST_CS6 .word 0x20010800 ;
ALL_ACCESS .word 0x3 ;
DOMAIN0 .word 0x0 ;
CACHEABLE .word 0x2 ;
NOT_CACHEABLE .word 0x0 ;
DOMAIN_VAL .word 0xFFFFFFFF ;
MASK_ADD .word 0x00003FFF ;
MASK_TTB .word 0xFFFFC000 ;
MASK_TTB_1ST .word 0xFFFFFC00 ;
MASK_PHYS .word 0xFFF00000 ;
MASK_PHYSICAL .word 0xFFFF0000 ;
MASK_VIRTUAL .word 0x000FF000 ;
ap0 .word 0x3 ;
ap1 .word 0x3 ;
ap2 .word 0x3 ;
ap3 .word 0x3 ;
;; ===========================================================================================
;; ===========================================================================================
;; ===========================================================================================
GPIO_IO_CNTL .word 0xFFFCE008
GPIO_IN .word 0xFFFCE000
addrSlowConfRegCS0 .word 0xFFFECC10
addrSlowConfRegCS3 .word 0xFFFECC1C
addrMifReg .word 0xFFFECC0C
BusWidthMask .word 0x00100000
; 0000_0000_00 0 1
valueSlowConfRegCS0_32bits .word 0x00304069 ; [b XXXX_XXXX_XX(1)(1)_X(000)_(0111)_(0000)_(1110)_X(0)(01)]
; FL BW RDMODE PGWST WRWST RDWST RT FCLKDIV
valueSlowConfRegCS3_32bits .word 0x00101178 ; [b XXXX_XXXX_XX(0)(1)_X(000)_(0001)_(0001)_(0111)_X(0)(00)]
; for 84MHz ; FL BW RDMODE PGWST WRWST RDWST RT FCLKDIV
; for a ROm to 70ns response time with a marge of 20ns: at 11.9ns (84MHz) -> 90ns = 7.56 ~ 8 periods so 7 RDWST
ArmBootModeMask .word 0x00000002
BurstReadMask .word 0x00040000
addrClkrst_IDLECT2 .word 0xFFFECE08
valueClkrst_IDLECT2 .word 0xFFFFFFFF
addrARM_CKCTL .word 0xFFFECE00
DSPCLK_DISABLE_MSK .word 0x00002000
ARM_GPIO_CLK_POS .word 0x00000200
AddrEmifFast .word 0xFFFECC20
;ValueEmifFast .word 0x0C020BF4 ; SDRAM 256 Mbit
;ValueEmifFast .word 0x0C020BB4 ; SDRAM 128 Mbit
ValueEmifFast .word 0x0D039174 ;;with auto refresh counter =913 =0x0391
;; 912.5 = 64 * 84 /4.096 - 400( for 84MHZ on TC )
;ValueEmifFast .word 0x0D044C74 ;;with auto refresh counter =1100 =0x044C
; ;; 1100 = 64 * 96 /4.096 - 400( for 96MHZ on TC )
;ValueEmifFast .word 0x0C020B74 ; SDRAM 64 Mbit
;ValueEmifFast .word 0x0C000474
;; MIF_SELF_REFRESH_DISABLE
;; 0,
;; MIF_AUTO_REFRESH_ENABLE,
;; 7, SDRAM type: 64 Meg
;; 523, Counter
;; MIF_SDRAM_FREQ_0,
;; MIF_POWER_DOWN_ENABLE,
;; MIF_SDRAM_CLOCK_ENABLE
;;
AddrEmifFastMRS .word 0xFFFECC24
;ValueEmifFastMRS .word 0x00000037
ValueEmifFastMRS .word 0x00000027
;; burst full-page lenght
;; cas latency = 3
ARM_SYSST_reg .word 0xFFFECE18
; bit 12 allows to select the synchronous scalable mode
ARM_SYSST_val .word 0x00001000
BIT12 .word 0x00001000
MIF_CS0_reg .word 0xFFFECC10
MIF_CS1_reg .word 0xFFFECC14
MIF_CS2_reg .word 0xFFFECC18
MIF_CS3_reg .word 0xFFFECC1C
MIF_DIV_BY2_MASK .word 0x00000002
ARM_CKCTL_reg .word 0xFFFECE00
ARM_CKCTL_val .word 0x00005115
;;
;; With this value of ARM_CKCTL, DSP CK is disabled,
;; and all prescalers are set to 1
;;
ARM_CKCTL_everyone_div_1 .word 0x00001000
;;
;; With this value of ARM_CKCTL, DSP CK is disabled,
;; TC is CK3/2, ARMPER is CK1/4.
;;
ARM_CKCTL_val_led .word 0x00001102
TC_Mask .word 0x00000300
AddrDpll .word 0xFFFECF00
BaseDpll .word 0x00003010
ValueDpll .word 0x00003A32 ;; x10 (x20 /2)
;; multp div
;ValueDpll .word 0x00003812 ;; [b 0011_(1000_0)(00)1_0010] : mult 16 ------ div 1 for 192MHz
; ;; multp div
;ValueDpll .word 0x00003892 ;; [b 0011_(1000_1)(00)1_0010] : mult 17 ------ div 1 for 204MHz
;; multp div
;ValueDpll .word 0x00003A32 ;; mult 20 ------ div 2
;ValueDpll .word 0x00003F52 ;; mult 30 ------ div 3
;; 120 Mhz m=20 d=2
.state32
;
; INT_Swi(unsigned stack, unsigned stackSize)
; R0 R1
;
; Enable exception and set up a stack
; Works only if called from 16-bit (THUMB) mode
;
;
INT_Swi:
LDRH r4, [LR, #-2] ; retrieve SWI parameter
AND r4, r4, #0xFF ; keep the argument only
CMP r4, #0xFA
BEQ SetSupervisor
CMP r4, #0xFB
BEQ SetUser
CMP r4, #0xFC
BEQ EnableFIQ
CMP r4, #0xFD
BEQ EnableIRQ
CMP r4, #0xF5
BEQ Set_SVC_Stack
CMP r4, #0xF4
BEQ Set_AbortD_Stack
CMP r4, #0xF0
BEQ SetIRQBit
CMP r4, #0xF1
BEQ ClearIRQBit
CMP r4, #0xF2
BEQ SetFIQBit
CMP r4, #0xF3
BEQ ClearFIQBit
B ExitSwi ; not handled
SetSupervisor:
MRS r7, SPSR ; Take a copy of Program Status Register
BIC r7,r7,#MODE_MASK ; Clear the mode bits
ORR r7,r7,#SUP_MODE ; Set Supervisor Mode
MSR SPSR, r7 ; Write back the modified SPSR
B ExitSwi ; not handled
SetUser:
MRS r7, SPSR ; Get copy of Program Status Register
BIC r7, r7, #MODE_MASK ; Clear mode bits
ORR r7, r7, #USR_MODE ; Set User Mode
MSR SPSR, r7 ; Write back modified SPSR
B ExitSwi ; not handled
EnableIRQ:
MOV r5, #IRQ_MODE
MOV r6, #IRQ_MASK
B DoIt
EnableFIQ:
MOV r5, #FIQ_MODE
MOV r6, #FIQ_MASK
B DoIt
Set_SVC_Stack:
;STACK MANIPULATION
MOV SP, r0 ; stack address
MOV r1,r1,lsl #2 ; convertion from word size to byte size
ADD SP, r1, SP ; add size to get initial SP
B ExitSwi
Set_AbortD_Stack:
MRS r2, CPSR
BIC r2, r2, #MODE_MASK
ORR r2, r2, #ABORT_MODE
MSR CPSR, r2 ; set abort mode
;STACK MANIPULATION
MOV SP, r0 ; stack address
MOV r1,r1,lsl #2 ; convertion from word size to byte size
ADD SP, r1, SP ; add size to get initial SP
BIC r2, r2, #MODE_MASK
ORR r2, r2, #SUP_MODE
MSR CPSR, r2 ; restore supervisor mode
B ExitSwi
SetIRQBit:
MOV r5, #IRQ_MASK
MOV r6, #SET_BIT
B SetClearFIQIRQ
ClearIRQBit:
MOV r5, #IRQ_MASK
MOV r6, #CLEAR_BIT
B SetClearFIQIRQ
SetFIQBit:
MOV r5, #FIQ_MASK
MOV r6, #SET_BIT
B SetClearFIQIRQ
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