📄 intvecs_led.asm
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;******************************************************************************
; TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
;
; Property of Texas Instruments
; For Unrestricted Internal Use Only
; Unauthorized reproduction and/or distribution is strictly prohibited.
; This product is protected under copyright law and trade secret law
; as an unpublished work.
;
; Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
;
;
;*******************************************************************************
.state32
.global _reset
.global _c_int00
.global _EX_AbortD
.global _EX_Irq
.global _EX_Fiq
.global INT_Swi
.global $INT_SetSupervisor
.global $INT_SetUser
.global $DMA_WriteConfig
.global $INT_EnableIRQ
.global $INT_EnableFIQ
.global $INT_SetIRQBit
.global $INT_ClearIRQBit
.global $INT_SetFIQBit
.global $INT_ClearFIQBit
.global $PEGA_DMA_WriteConfig
.global $INT_SetLeadMmuTtbl
.global $INT_DisableResetLeadMmu
.global $INT_EnableLeadMmu
.global $INT_Set_SVC_Stack
.global $INT_Set_AbortD_Stack
.global $BOOT_Fast
.global $DisableCache_prefetch
.include "mmu_mac.asm"
.sect ".intvecs"
_reset B initBasic ; RESET INTERRUPT
undef: B undef ; UNDEFINED INSTRUCTION INTERRUPT
B INT_Swi ; SOFTWARE INTERRUPT
abort1: B abort1 ; ABORT (PREFETCH) INTERRUPT
B _EX_AbortD ; ABORT (DATA) INTERRUPT
reserv: B reserv ; RESERVED
B _EX_Irq ; IRQ INTERRUPT
B _EX_Fiq ; FIQ INTERRUPT
GPIO_TDL_LED_PIN .equ 0x01 ; Gpio pin 0 to read
GPIO_CLOCKENABLE .equ 0x02 ; Gpio pin 1 to read
JTAGVER .equ 3 ; JTAG version
LOCKOUT .equ 0xC0 ; Interrupt lockout value
IRQ_MASK .equ 0x80 ; IRQ mask value
FIQ_MASK .equ 0x40 ; FIQ mask value
MODE_MASK .equ 0x1F ; Processor Mode Mask
FIQ_MODE .equ 0x11 ; Fast Interrupt Mode (FIQ)
IRQ_MODE .equ 0x12 ; Interrupt Mode (IRQ)
SUP_MODE .equ 0x13 ; Supervisor Mode
USR_MODE .equ 0x10 ; User Mode
ABORT_MODE .equ 0x17 ; Abort Mode
SYS_MODE .equ 0x1F ; System mode
CLEAR_BIT .equ 0x00 ; Clear Bit
SET_BIT .equ 0x01 ; Set Bit
.text
; Basic Initializations
initBasic:
;; -------Flush Instruction cache-------
;; --------------------------------------
;; -------usefull for led ---------------
;; --------------------------------------
MOV r1,#0
MCR p15, #0, r1, c7, c5 ; Flush Instruction Cache
;; -------Enable Instruction cache-------
;; --------------------------------------
MRC p15, #0, R1, C1, C0
ORR R1, R1, #0x1000
MCR P15, #0, R1, C1, C0
;; --------------------------------------
;; --------------------------------------
; Initialize Emif Slow Chip-Select Config register
LDR r0, addrSlowConfRegCS0 ; Load into r0 address of slow config reg CS0
LDR r4, addrSlowConfRegCS3 ; Load into r4 address of slow config reg CS3
LDR r1, valueSlowConfRegCS0_32bits ; Load into r1 value of slow config reg CS0
LDR r5, valueSlowConfRegCS3_32bits ; Load into r5 value of slow config reg CS3
; Check romsize to set a correct value in SlowConfRegCS0_32bits
LDR r2, [r0]
; Get the value of the register at reset
LDR r3, BusWidthMask ; Load the mask to test bit
TST r2, r3 ; Test if romsize is in 32 bits or in 16 bits
BNE SET_EMIF ; If in 32 bits the value of SlowConfRegCS0_32bits
; is correct otherwise clear the bit BW
BUS_16:
BIC r1, r1,r3 ; Clear bit BW
BIC r5, r5,r3 ; Clear bit BW
SET_EMIF:
STR r1, [r0] ; Store value into address of slow config reg CS 0
STR r5, [r4] ; Store value into address of slow config reg CS 3
; SDRAM initialisation
LDR R0, AddrEmifFast
LDR R1, ValueEmifFast
STR R1, [R0]
LDR R0, AddrEmifFastMRS
LDR R1, ValueEmifFastMRS
STR R1, [R0]
;SET_EMIF:
; LDR r3, addrMifReg ; Load into r3 address of slow interface config reg
; LDR r2, [r3] ; Get the value of the register at reset
; LDR r3, ArmBootModeMask ; Load the mask to test bit
; TST r2, r3 ; Test if BOOT MODE is set
; BNE OVERLAY_MODE ; If BOOT MODE = 1 branch to OVERLAY_MODE tag
;NOT_OVERLAY_MODE:
; LDR r2, [r0] ; Get back the value of the config register at reset
; LDR r3, BurstReadMask
; TST r2,r3 ; If CS0 is in burst mode the CS is already initialize
; BNE CS_INITIALIZED ; Else the CS is setup
; RTL Debug (Set wait state to minimum value to speed up the simulations)
; STR r1, [r0] ; Store value into address of slow config reg CS 0
; B CS_INITIALIZED ; Branch to CS_INITIALIZED tag
;
;OVERLAY_MODE:
; LDR r2, [r4] ; Get back the value of the register at reset
; LDR r3, BurstReadMask
; TST r2,r3 ; If CS3 is in burst mode the CS is already initialize
; BNE CS_INITIALIZED ; Else the CS is setup
; RTL Debug (Set wait state to minimum value to speed up the simulations)
; STR r5, [r4] ; Store value into address of slow config reg CS 3
CS_INITIALIZED:
; Enable ARM GPIO Clock
LDR R1,ARM_GPIO_CLK_POS ; load ARM GPIO Clock bit position
LDR R2,addrClkrst_IDLECT2 ; load ARM CLKM IDLECT2 register address
LDR R3, [R2] ; Get back the value of the ARM CLKM IDLECT2 register
ORR R3,R3,R1 ; Set the ARM GPIO Clock enable bit
STR R3,[R2] ; Write the ARM CLKM IDLECT2 register
GPIO_READ_CLOCK120MHZ:
MOV R2,#GPIO_CLOCKENABLE
LDR R3,GPIO_IN ; load adress of GPIO_IN in r3
LDR R4,[R3]
AND R3,R4,R2 ; value of the signal on the GPIO_IN is in R3
CMP R3,#0x00
BNE RUN_PROG2
; Set the synchronous scalable mode
LDR r0,ARM_SYSST_reg
LDR R1,ARM_SYSST_val
STR R1,[R0]
; Set the SMIF CS1 clock divider by 2
LDR R1,MIF_DIV_BY2_MASK
LDR R0,MIF_CS1_reg
LDR R2,[R0]
BIC R2,R2,R1
STR R2,[R0]
; Set the SMIF CS2 clock divider by 2
LDR R0,MIF_CS2_reg
LDR R2,[R0]
BIC R2,R2,R1
STR R2,[R0]
TEST_LED_MODE:
MOV R2,#GPIO_TDL_LED_PIN ;; R2 contains LED pin (GPIO0) position = 0x0000001
LDR R3,GPIO_IN ;; load adress of GPIO_IN in r3
LDR R4,[R3] ;; R4 contains values of GPIOs
AND R3,R4,R2 ;; R3 contains LED_PIN value
CMP R3,#0x00 ;; If 0 (functionnal)
BEQ INIT_DPLL_NO_LED ;; Branch to functionnal init
;
; Initialize DPLL in LED mode
;
INIT_DPLL_LED:
;
; Get the constants
; and set the dpll with the value read
;
LDR R0, AddrDpll ;; R0 contains DPLL control register address
LDR R1, AddrDpllLed ;; R1 contains address where DPLL parameter is passed
LDR R2, [R1] ;; R2 contains DPLL control value
MOV R6, R2, LSR #0x08 ;; R6 is R2 shifted right of 8 bits
MOV R4, R6, LSR #0x04 ;; R4 contains R6 shifted right of 4 bits
AND R4, R4, #0x01 ;; R4 contains DSP bit
MOV R7, R6, LSR #0x01 ;; R7 contains R6 shifted right of 1 bit
AND R7, R7, #0x01 ;; R7 contains TC bit
MOV R8, R6, LSR #0x02 ;; R8 contains R6 shifted right of 2 bit
AND R8, R8, #0x01 ;; R8 contains ARM bit
AND R5, R6, #0x01 ;; R5 contains MODE bit
CMP R5, #0x01 ;; If MODE = 1 -> synchronous scalable
BEQ SET_SYNC_SCALABLE ;; Branch to synchronous scalable routine
;
; Initialize CLK CTRL in FULL_SYNCHRONOUS
;
SET_SYNCHRONOUS:
LDR R3, ARM_CKCTL_reg ;; Sets CKCTL reg
LDR R5, ARM_CKCTL_everyone_div_1 ;; To same div for everyone
ORR R5, R5, R4, LSL #0x0D ;; Set DSP enable bit if needed
STR R5, [R3]
LDR R3, ARM_SYSST_reg ;; Get ARM_SYSST address
LDR R4, [R3] ;; Get ARM_SYSST value
LDR R5, BIT12 ;; R5 contains BIT12
BIC R4, R4, R5 ;; Clear bit 12 (Full synchronous mode)
STR R4, [R3] ;; Store new value in ARM_SYSST
B SET_DPLL_LED ;; Sets DPLL for LED
;
; Initialize CLK CTRL in SYNCHRONOUS SCALABLE
;
SET_SYNC_SCALABLE:
LDR R3, ARM_CKCTL_reg
LDR R5, ARM_CKCTL_val_led ;; R4 contains basic value to put in DPLL register
ORR R5, R5, R4, LSL #0x0D ;; If R4 is 1, set DSP enable bit
ORR R5, R5, R8, LSL #0x04 ;; If R8 is 1, set ARM divide by 2
EOR R5, R5, R7, LSL #0x08 ;; If R7 is 1, invert TC divider LSB
EOR R5, R5, R7, LSL #0x09 ;; If R7 is 1, invert TC divider MSB
STR R5, [R3]
;
; Sets DPLL in LED mode
;
SET_DPLL_LED:
AND R6, R2, #0x07 ;; R6 contains R2 3 LSB (-> PLL_DIV+1)
SUB R6, R6, #0x01 ;; R6 contains PLL_DIV
AND R6, R6, #0x03 ;; Get rid of carry (if any... will maybe be handled gracefully someday)
AND R5, R2, #0xF8 ;; R5 contains R2 5 next bits (-> PLL_MULT(4:0) | 000 )
ORR R6, R6, R5, LSR #0x01 ;; R6 contain PLL_MULT(4:0) | PLL_DIV(1:0)
LDR R4, BaseDpll ;; Store 0x3010 into R4 (0011000000010000). The seven zeros will be replaced by mult/div
ORR R6, R4, R6, LSL #0x05 ;; R6 contains 0011 | PLL_MULT(4:0) | PLL_DIV(1:0) | 10000 -> DPLL control value
STRH R6, [R0] ;; Store DPLL control value in DPLL control register
B RUN_PROG2 ;; Skip functionnal init
;
; Initialize DPLL in functional (not LED) mode
;
INIT_DPLL_NO_LED:
; Set Clock divider tree and turn off DSP clock
LDR R0,ARM_CKCTL_reg
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