nand_flash.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC9,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC9,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_RESET,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_RESET,RESETDMASYNCHRO,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_RESET,RESET_ECC,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_FIFOCTRL,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_FIFOCTRL,FIFO_SIZE,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_FIFOCTRL,BLOCK_COUNT,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_PSC_CLK,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_PSC_CLK,PSC_CLK,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_SYSTEST,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSTEST,TEST_UNLOCK,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSTEST,MAP,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSTEST,ACCESS,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSTEST,ALLOW_INIT,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_SYSCFG,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSCFG,SOFTRESET,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_SYSCFG,AUTOIDLE,32);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : NFLA_TestRegistersAccess
//
// DESCRIPTION : Test the access to NAND_FLASH registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void NFLA_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    // Can't perform write/read access to NND_ACCESS register if there is no command sent
    //BEGIN_RW_TEST(NAND_FLASH_NND_ACCESS,32);
    //RW_PREPARE_WRITE(NAND_FLASH_NND_ACCESS,NND_ACCESS,32);
    //RW_WRITE(NAND_FLASH_NND_ACCESS);
    //RW_TEST_READ(NAND_FLASH_NND_ACCESS,NND_ACCESS,32);
    //RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_ACCESS);
    //END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_ADDR_SRC,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_ADDR_SRC,NND_ADDR_SRC,32);
    RW_WRITE(NAND_FLASH_NND_ADDR_SRC);
    RW_TEST_READ(NAND_FLASH_NND_ADDR_SRC,NND_ADDR_SRC,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_ADDR_SRC);
    END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_CTRL,32);
    //NAND_FLASH_NND_CTRL,RESERVED_0 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,PREFETCH,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,POSTWRITE,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,WRITEPROT3,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,CHIPEN3,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,WRITEPROT2,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,CHIPEN2,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,WRITEPROT1,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,CHIPEN1,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,WRITEPROT0,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,CHIPEN0,32);
    //NAND_FLASH_NND_CTRL,RESERVED_1 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,ADDRCNT,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,A8,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,BE,32);
    //NAND_FLASH_NND_CTRL,RESERVED_2 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,ECC_256,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_CTRL,ECC_ON,32);
    RW_WRITE(NAND_FLASH_NND_CTRL);
    //NAND_FLASH_NND_CTRL,RESERVED_0 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_CTRL,PREFETCH,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,POSTWRITE,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,WRITEPROT3,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,CHIPEN3,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,WRITEPROT2,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,CHIPEN2,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,WRITEPROT1,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,CHIPEN1,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,WRITEPROT0,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,CHIPEN0,32);
    //NAND_FLASH_NND_CTRL,RESERVED_1 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_CTRL,ADDRCNT,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,A8,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,BE,32);
    //NAND_FLASH_NND_CTRL,RESERVED_2 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_CTRL,ECC_256,32);
    RW_TEST_READ(NAND_FLASH_NND_CTRL,ECC_ON,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_CTRL);
    END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_MASK,32);
    //NAND_FLASH_NND_MASK,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_MASK,MSK_EMPTY,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_MASK,MSK_FULL,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_MASK,MSK_COUNT,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_MASK,MSK_READY,32);
    RW_WRITE(NAND_FLASH_NND_MASK);
    //NAND_FLASH_NND_MASK,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_MASK,MSK_EMPTY,32);
    RW_TEST_READ(NAND_FLASH_NND_MASK,MSK_FULL,32);
    RW_TEST_READ(NAND_FLASH_NND_MASK,MSK_COUNT,32);
    RW_TEST_READ(NAND_FLASH_NND_MASK,MSK_READY,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_MASK);
    END_RW_TEST();
 
    /*
    // Can't be tested as bits are R/W1C
    BEGIN_RW_TEST(NAND_FLASH_NND_STATUS,32);
    //NAND_FLASH_NND_STATUS,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_STATUS,FIFO_EMPTY,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_STATUS,FIFO_FULL,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_STATUS,COUNT_ZERO,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_STATUS,READY_EVENT,32);
    RW_WRITE(NAND_FLASH_NND_STATUS);
    //NAND_FLASH_NND_STATUS,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_STATUS,FIFO_EMPTY,32);
    RW_TEST_READ(NAND_FLASH_NND_STATUS,FIFO_FULL,32);
    RW_TEST_READ(NAND_FLASH_NND_STATUS,COUNT_ZERO,32);
    RW_TEST_READ(NAND_FLASH_NND_STATUS,READY_EVENT,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_STATUS);
    END_RW_TEST();
    */

    BEGIN_RW_TEST(NAND_FLASH_NND_COMMAND,32);
    //NAND_FLASH_NND_COMMAND,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_COMMAND,COMMAND,32);
    RW_WRITE(NAND_FLASH_NND_COMMAND);
    //NAND_FLASH_NND_COMMAND,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_COMMAND,COMMAND,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_COMMAND);
    END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_COMMAND_SEC,32);
    //NAND_FLASH_NND_COMMAND_SEC,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_COMMAND_SEC,COMMAND_SEC,32);
    RW_WRITE(NAND_FLASH_NND_COMMAND_SEC);
    //NAND_FLASH_NND_COMMAND_SEC,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_COMMAND_SEC,COMMAND_SEC,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_COMMAND_SEC);
    END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_ECC_SELECT,32);
    //NAND_FLASH_NND_ECC_SELECT,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_ECC_SELECT,ECC_SELECT,32);
    RW_WRITE(NAND_FLASH_NND_ECC_SELECT);
    //NAND_FLASH_NND_ECC_SELECT,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_ECC_SELECT,ECC_SELECT,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_ECC_SELECT);
    END_RW_TEST();

    /*
    // Can't be tested because the 2 bits are automaically reseted
    BEGIN_RW_TEST(NAND_FLASH_NND_RESET,32);
    //NAND_FLASH_NND_RESET,RESERVED_0 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_RESET,RESETDMASYNCHRO,32);
    //NAND_FLASH_NND_RESET,RESERVED_1 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_RESET,RESET_ECC,32);
    RW_WRITE(NAND_FLASH_NND_RESET);
    //NAND_FLASH_NND_RESET,RESERVED_0 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_RESET,RESETDMASYNCHRO,32);
    //NAND_FLASH_NND_RESET,RESERVED_1 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_RESET,RESET_ECC,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_RESET);
    END_RW_TEST();
    */

    BEGIN_RW_TEST(NAND_FLASH_NND_FIFOCTRL,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_FIFOCTRL,FIFO_SIZE,32);
    //NAND_FLASH_NND_FIFOCTRL,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_FIFOCTRL,BLOCK_COUNT,32);
    RW_WRITE(NAND_FLASH_NND_FIFOCTRL);
    RW_TEST_READ(NAND_FLASH_NND_FIFOCTRL,FIFO_SIZE,32);
    //NAND_FLASH_NND_FIFOCTRL,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_FIFOCTRL,BLOCK_COUNT,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_FIFOCTRL);
    END_RW_TEST();

    BEGIN_RW_TEST(NAND_FLASH_NND_PSC_CLK,32);
    //NAND_FLASH_NND_PSC_CLK,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_PSC_CLK,PSC_CLK,32);
    RW_WRITE(NAND_FLASH_NND_PSC_CLK);
    //NAND_FLASH_NND_PSC_CLK,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_PSC_CLK,PSC_CLK,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_PSC_CLK);
    END_RW_TEST();

    /*
    // Can't be tested because there is a special way to write into this register:
    // set bit 7 (test_unlock)
    // then enable others bits and keep bit 7 to 1
    // This module will be used when using test mode of nand_flash controller
    BEGIN_RW_TEST(NAND_FLASH_NND_SYSTEST,32);
    //NAND_FLASH_NND_SYSTEST,RESERVED_0 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSTEST,TEST_UNLOCK,32);
    //NAND_FLASH_NND_SYSTEST,RESERVED_1 is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSTEST,MAP,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSTEST,ACCESS,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSTEST,ALLOW_INIT,32);
    RW_WRITE(NAND_FLASH_NND_SYSTEST);
    //NAND_FLASH_NND_SYSTEST,RESERVED_0 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_SYSTEST,TEST_UNLOCK,32);
    //NAND_FLASH_NND_SYSTEST,RESERVED_1 is Read Only
    RW_TEST_READ(NAND_FLASH_NND_SYSTEST,MAP,32);
    RW_TEST_READ(NAND_FLASH_NND_SYSTEST,ACCESS,32);
    RW_TEST_READ(NAND_FLASH_NND_SYSTEST,ALLOW_INIT,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_SYSTEST);
    END_RW_TEST();
    */

    /*
    // Can't be tested because by writing '1' to SoftReset bit, 
    // the soft reset sequence starts
    BEGIN_RW_TEST(NAND_FLASH_NND_SYSCFG,32);
    //NAND_FLASH_NND_SYSCFG,RESERVED is Read Only
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSCFG,SOFTRESET,32);
    RW_PREPARE_WRITE(NAND_FLASH_NND_SYSCFG,AUTOIDLE,16);
    RW_WRITE(NAND_FLASH_NND_SYSCFG);
    //NAND_FLASH_NND_SYSCFG,RESERVED is Read Only
    RW_TEST_READ(NAND_FLASH_NND_SYSCFG,SOFTRESET,32);
    RW_TEST_READ(NAND_FLASH_NND_SYSCFG,AUTOIDLE,32);
    RW_WRITE_PREVIOUS_VALUE(NAND_FLASH_NND_SYSCFG);
    END_RW_TEST();
    */

  END_ACCESS_MODULE();

}