nand_flash.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : nand_flash.c
//
//   Date of Module Modification:6/13/02
//   Date of Generation :6/25/02
//
//   Author : Sebastien Sabatier
//
//===============================================================================
#include "global_types.h"
#include "nand_flash.h"
#include "testaccess.h"

#include "result.h"
#include "test.h"
#include "mapping.h"
#include "errorcodes.h"

//---------------------------------------------------------------------
// NAME        : NAND_FLASH_TestResetValue
//
// DESCRIPTION : Test the reset values of NAND_FLASH registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void NFLA_TestResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(NAND_FLASH_NND_REVISION,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_REVISION,NND_REVISION,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ACCESS,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ACCESS,NND_ACCESS,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ADDR_SRC,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ADDR_SRC,NND_ADDR_SRC,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_CTRL,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,PREFETCH,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,POSTWRITE,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,WRITEPROT3,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,CHIPEN3,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,WRITEPROT2,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,CHIPEN2,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,WRITEPROT1,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,CHIPEN1,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,WRITEPROT0,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,CHIPEN0,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,ADDRCNT,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,A8,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,BE,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,ECC_256,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_CTRL,ECC_ON,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_MASK,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_MASK,MSK_EMPTY,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_MASK,MSK_FULL,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_MASK,MSK_COUNT,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_MASK,MSK_READY,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_STATUS,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_STATUS,FIFO_EMPTY,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_STATUS,FIFO_FULL,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_STATUS,COUNT_ZERO,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_STATUS,READY_EVENT,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_READY,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_READY,READY,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_COMMAND,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_COMMAND,COMMAND,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_COMMAND_SEC,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_COMMAND_SEC,COMMAND_SEC,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC_SELECT,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC_SELECT,ECC_SELECT,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC1,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC1,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC2,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC2,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC3,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC3,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC4,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC4,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC5,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC5,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC6,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC6,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC7,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P2048O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P1024O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P512O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P256O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P128O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P64O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P32O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P16O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P8O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P4O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P2O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P1O,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P2048E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P1024E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P512E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P256E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P128E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P64E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P32E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P16E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P8E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P4E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P2E,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC7,P1E,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(NAND_FLASH_NND_ECC8,32);
    TEST_FIELD_RESET(NAND_FLASH_NND_ECC8,P2048O,32);