dma.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

*/
void DMA_SetControlReg
           (const DMA_ChannelId_t              ChannelId,
            const DMA_Priority_t               Priority,
            const DMA_SourcePort_t             SourcePort,
            const DMA_DestinationPort_t        DestinationPort,
            const DMA_TransferWidth_t          TransferWidth,
            const DMA_SourceAddressMode_t      SourceAddressMode,
            const DMA_DestinationAddressMode_t DestinationAddressMode,
            const DMA_Autoinit_t               Autoinit,
            const DMA_Synchro_t                Synchro,
            const DMA_Channel_State_t          Channel_State,
            const DMA_BusErrorIE_t             BusErrorIE,
            const DMA_BlockTrIE_t              BlockTrIE,
            const DMA_HalfBlockTrIE_t          HalfBlockTrIE,
            const DMA_DropIE_t                 DropIE)
{
UWORD32 value;

  /* extract all the fields but Priority */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_PRIO_MSK;
  /* add field contents into register */
  value |= Priority;

  value &= ~DMA_SRC_PORT_MSK;
  value |= (SourcePort << DMA_SRC_PORT_BITPOS);

  value &= ~DMA_DST_PORT_MSK;
  value |= (DestinationPort << DMA_DST_PORT_BITPOS);

  value &= ~DMA_TRANSFERT_WIDTH_MSK;
  value |= (TransferWidth << DMA_TRANSFERT_WIDTH_BITPOS);

  value &= ~DMA_SRC_ADDR_MODE_MSK;
  value |= (SourceAddressMode << DMA_SRC_ADDR_MODE_BITPOS);

  value &= ~DMA_DST_ADDR_MODE_MSK;
  value |= (DestinationAddressMode << DMA_DST_ADDR_MODE_BITPOS);

  value &= ~DMA_AUTOINIT_MSK;
  value |= (Autoinit << DMA_AUTOINIT_BITPOS);

  value &= ~DMA_SYNCHRO_MSK;
  value |= (Synchro << DMA_SYNCHRO_BITPOS);

  value &= ~DMA_ENABLE_CHANNEL_MSK;
  value |= (Channel_State << DMA_ENABLE_CHANNEL_BITPOS);

  value &= ~DMA_BUS_ERROR_IE_MSK;
  value |= (BusErrorIE << DMA_BUS_ERROR_IE_BITPOS);

  value &= ~DMA_BLOCK_TR_IE_MSK;
  value |= (BlockTrIE << DMA_BLOCK_TR_IE_BITPOS);

  value &= ~DMA_HALF_BK_IE_MSK;
  value |= (HalfBlockTrIE << DMA_HALF_BK_IE_BITPOS);

  value &= ~DMA_DROP_IE_MSK;
  value |= (DropIE << DMA_DROP_IE_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}


/*
--------------------------------------------------------------------
            DMA_GetCondBitsInterrupt                               -
--------------------------------------------------------------------
*/
void DMA_GetCondBitsInterrupt
           (DMA_ChannelId_t const ChannelId,
            boolean_t       *const TimeoutBuserrorRaised,
            boolean_t       *const BlockCompleted,
            boolean_t       *const HalfBlockCompleted,
            boolean_t       *const SyncEventDropped)
{
UWORD32 MemReg;
  /* Read DMA Channel control register */ 
  MemReg = *(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr;
  /* Store all the read condition bits */
  *TimeoutBuserrorRaised = (boolean_t)((MemReg & DMA_BUS_ERROR_COND_MSK)
                           >> DMA_BUS_ERROR_COND_BITPOS);
  *BlockCompleted        = (boolean_t)((MemReg & DMA_BLOCK_TR_COND_MSK) 
                           >> DMA_BLOCK_TR_COND_BITPOS);
  *HalfBlockCompleted    = (boolean_t)((MemReg & DMA_HALF_BK_COND_MSK) 
                           >> DMA_HALF_BK_COND_BITPOS);
  *SyncEventDropped    = (boolean_t)((MemReg & DMA_DROP_COND_MSK) 
                           >> DMA_DROP_COND_BITPOS);
  /* reset all the condition bits after reading */
  MemReg &= DMA_CLEAR_ALL_CONDBITS;
  /* Update the DMA channel control register */
  *(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr = MemReg;
}

void DMA_GetFifoStatus(DMA_ChannelId_t const ChannelId,
            	       boolean_t       *const FifoNotEmpty,
                       UWORD8          *const FifoBytesLeft)
{
UWORD32 MemReg;
  /* Read DMA Channel control register */ 
  MemReg = *(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr;
  /* Store all the read condition bits */

  *FifoNotEmpty = (boolean_t)((MemReg & DMA_FIFO_STATUS_MSK) >> DMA_FIFO_STATUS_BITPOS);
  *FifoBytesLeft= (MemReg & DMA_FIFO_BYTES_LEFT_MSK) >> DMA_FIFO_BYTES_LEFT_BITPOS;
}

UWORD32 DMA_ReadFifo(DMA_ChannelId_t const ChannelId)
{
  /* Read DMA Channel control register */ 
return(*(UWORD32*)RegisterAddrUsr[ChannelId].dma_fifo);
}

/*
-------------------------------------------------------------------------
               DMA_GetNextWriteAddress                                  -
-------------------------------------------------------------------------
*/
UWORD16 DMA_GetNextWriteAddress(DMA_ChannelId_t const ChannelId)
{
return 
  (  *(UWORD32*)RegisterAddrSup[ChannelId].dma_bkc 
   & DMA_NEXT_WRITE_ADD_MSK) >> DMA_BUS_ERROR_COND_BITPOS;
}


/*
--------------------------------------------------------------
            DMA_SetPortSource                                -
--------------------------------------------------------------
*/
void DMA_SetPortSource(const DMA_ChannelId_t   ChannelId,
                       const DMA_SourcePort_t  SourcePort)
{
UWORD32 value;
  /* extract all the fields but PortSource */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_SRC_PORT_MSK;
  /* add field contents into register */
  value |= (SourcePort << DMA_SRC_PORT_BITPOS);
  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}

/*
--------------------------------------------------------------
            DMA_SetPortDest                                  -
--------------------------------------------------------------
*/
void DMA_SetPortDest(const DMA_ChannelId_t   ChannelId,
                     const DMA_SourcePort_t  DestPort)
{
UWORD32 value;
  /* extract all the fields but PortSource */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_DST_PORT_MSK;
  /* add field contents into register */
  value |= (DestPort << DMA_DST_PORT_BITPOS);
  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}



/*
-----------------------------------------------------------------------
               DMA_SetSourceAddress                                   -
-----------------------------------------------------------------------
*/
void DMA_SetSourceAddress
       (const DMA_ChannelId_t   ChannelId,
        const DMA_SourcePort_t  SourcePort,
        const UWORD32        SourceAddress)
{
  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_src_add = SourceAddress;
}



/*
-----------------------------------------------------------------------
               DMA_SetDestAddress                                     -
-----------------------------------------------------------------------
*/
void DMA_SetDestAddress
       (const DMA_ChannelId_t       ChannelId,
        const DMA_DestinationPort_t DestinationPort,
        const UWORD32            DestinationAddress)
{
  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_dst_add = DestinationAddress;
}


/*
-----------------------------------------------------------------------
               DMA_SetRheaSourceAddress                               -
-----------------------------------------------------------------------
*/
void DMA_SetRheaSourceAddress
       (const DMA_ChannelId_t          ChannelId,
        const UWORD16               RheaAddr,
        const RHEA_Strobe0ChipSelect_t RheaChipSelect)
{
UWORD32 value = 0x00000000;
     value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_src_add 
             & ~DMA_SRC_DST_RHEA_ADDR_MSK & ~DMA_SRC_DST_RHEA_CS_MSK;
     value |=   (RheaAddr << DMA_SRC_DST_RHEA_ADDR_BITPOS)
              | (RheaChipSelect << DMA_SRC_DST_RHEA_CS_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_src_add = value;
}



/*
-----------------------------------------------------------------------
            DMA_SetRheaDestAddress                                    -
-----------------------------------------------------------------------
*/
void DMA_SetRheaDestAddress
       (const DMA_ChannelId_t           ChannelId,
        const UWORD16                RheaAddr,
        const RHEA_Strobe0ChipSelect_t  RheaChipSelect)
{
UWORD32 value = 0x00000000;
     value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_dst_add 
             & ~DMA_SRC_DST_RHEA_ADDR_MSK & ~DMA_SRC_DST_RHEA_CS_MSK;
     value |=   (RheaAddr << DMA_SRC_DST_RHEA_ADDR_BITPOS)
              | (RheaChipSelect << DMA_SRC_DST_RHEA_CS_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_dst_add = value;
}


/*
-----------------------------------------------------------------------
               DMA_SetBlockCount                                      -
-----------------------------------------------------------------------
*/
void DMA_SetBlockCount(const DMA_ChannelId_t  ChannelId,
                       const UWORD16          TransferLength)
{
UWORD32 value;
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_bkc & ~DMA_BLK_COUNT_MSK;
  value |= TransferLength;

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_bkc = value;
}


//-----------------------------------------------------------------------
//               DMA_SetLcdCtrolReg                                     -
//-----------------------------------------------------------------------
void DMA_SetLcdCtrolReg(const FrameMode_t               FrameMode,
                        const FrameInterruptEnable_t    FrameInterruptEnable,
                        const BusErrorInterruptEnable_t BusErrorInterruptEnable)
{
UWORD32 value ;
// read initial value
value = REG32(DMA_REG_LCD_CTROL_SUPERVISOR_ADDR);
// clear used bits
value = value & ~DMA_LCD_CTRL_MSK;
// set used bits
 value |= (FrameMode  << DMA_LCD_CTRL_FRAME_MODE_BITPOS) |
          (FrameInterruptEnable << DMA_LCD_CTRL_FRAME_IT_IE_BITPOS) |
          (BusErrorInterruptEnable << DMA_LCD_CTRL_BUS_ERROR_IE_BITPOS);
/* Commit the Register Update */
REG32(DMA_REG_LCD_CTROL_SUPERVISOR_ADDR) = value;
}
        

void DMA_GetLcdCondBitsInterrupt(boolean_t  *const Frame_1_It_Cond,
										   boolean_t  *const Frame_2_It_Cond,
										   boolean_t  *const Bus_Error_It_Cond)
										 
{
UWORD32 value ;
value = REG32(DMA_REG_LCD_CTROL_SUPERVISOR_ADDR);
if (value & DMA_LCD_CTRL_FRAME1_IT_COND_MSK)
	*Frame_1_It_Cond = True; 
else
	*Frame_1_It_Cond = False; 

if (value & DMA_LCD_CTRL_FRAME2_IT_COND_MSK)
	*Frame_2_It_Cond = True; 
else
	*Frame_2_It_Cond = False; 

if (value & DMA_LCD_CTRL_BUS_ERROR_IT_COND_MSK)
	*Bus_Error_It_Cond = True; 
else
	*Bus_Error_It_Cond = False; 

// reset the Condition bits
value &=  ~DMA_LCD_CTRL_FRAME1_IT_COND_MSK;
value &=  ~DMA_LCD_CTRL_FRAME2_IT_COND_MSK;
value &=  ~DMA_LCD_CTRL_BUS_ERROR_IT_COND_MSK;
REG32(DMA_REG_LCD_CTROL_SUPERVISOR_ADDR) = value;
}


/*
---------------------------------------------------------------------------
               DMA_SetLcdTopFrame1                                        -
---------------------------------------------------------------------------
*/
void DMA_SetLcdTopFrame1(const UWORD32 StartAddress)
{
REG32(DMA_REG_LCD_TOP_FRAME1_SUPERVISOR_ADDR) = (StartAddress & DMA_LCD_TOP_FRAME_MSK);
}

/*
---------------------------------------------------------------------------
               DMA_SetLcdTopFrame2                                        -
----------------------------------