dma.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  /* Goback to user mode after commit update of Registers */
  
}

/*
-----------------------------------------------------------------------------
               DMA_SendEmifToSdram                                          -
-----------------------------------------------------------------------------
*/
void DMA_SendEmifToSdram(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          	SourceAddress,
                         const UWORD32          	DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)

{
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_EMIF_SOURCE_PORT    , SourceAddress);
 DMA_SetDestAddress  (ChannelId, DMA_SDRAM_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_EMIF_SOURCE_PORT,
            DMA_SDRAM_DESTINATION_PORT,
            DMA_32BITS_TRANSFER_WIDTH, /* all access to SDRAM/EMIF/LOCAL in 32 bits */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}

/*
-----------------------------------------------------------------------------
               DMA_SendSdramToSdram                                          -
-----------------------------------------------------------------------------
*/
void DMA_SendSdramToSdram(const DMA_ChannelId_t     ChannelId,
                          const DMA_Priority_t      Priority,
                          const UWORD32             SourceAddress,
                          const UWORD32             DestinationAddress,
                          const UWORD16             TransferLength,
                          const DMA_Autoinit_t      AutoInitToggle,
                          const DMA_HalfBlockTrIE_t HalfBlockIE)

{
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_SDRAM_SOURCE_PORT    , SourceAddress);
 DMA_SetDestAddress  (ChannelId, DMA_SDRAM_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_SDRAM_SOURCE_PORT,
            DMA_SDRAM_DESTINATION_PORT,
            DMA_32BITS_TRANSFER_WIDTH, /* all access to SDRAM/EMIF/LOCAL in 32 bits */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
 //           DMA_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_DISABLE,
 //           DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}

/*
---------------------------------------------------------------------------
               DMA_SendEmifToLocal                                        -
---------------------------------------------------------------------------
*/
void DMA_SendEmifToLocal(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          SourceAddress,
                         const UWORD32          DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_EMIF_SOURCE_PORT, SourceAddress);
 DMA_SetDestAddress(ChannelId, DMA_LOCAL_IMIF_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_EMIF_SOURCE_PORT,
            DMA_LOCAL_IMIF_DESTINATION_PORT,
            /* all access to SDRAM/EMIF/LOCAL ports in 32 bits */
            DMA_32BITS_TRANSFER_WIDTH,
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}


/*
---------------------------------------------------------------------------
               DMA_SendLocalToEmif                                        -
---------------------------------------------------------------------------
*/
void DMA_SendLocalToEmif(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          SourceAddress,
                         const UWORD32          DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_LOCAL_IMIF_SOURCE_PORT, SourceAddress);
 DMA_SetDestAddress(ChannelId, DMA_EMIF_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_LOCAL_IMIF_SOURCE_PORT,
            DMA_EMIF_DESTINATION_PORT,
            /* all access to SDRAM/EMIF/LOCAL ports in 32 bits */
            DMA_32BITS_TRANSFER_WIDTH,
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}


/*
---------------------------------------------------------------------------
               DMA_SendLocalToLocal                                       -
---------------------------------------------------------------------------
*/
void DMA_SendLocalToLocal(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          SourceAddress,
                         const UWORD32          DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_LOCAL_IMIF_SOURCE_PORT, SourceAddress);
 DMA_SetDestAddress(ChannelId, DMA_LOCAL_IMIF_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_LOCAL_IMIF_SOURCE_PORT,
            DMA_LOCAL_IMIF_DESTINATION_PORT,
            /* all access to SDRAM/EMIF/LOCAL ports in 32 bits */
            DMA_32BITS_TRANSFER_WIDTH,
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}



/*
---------------------------------------------------------------------------
               DMA_SendSdramToLocal                                       -
---------------------------------------------------------------------------
*/
void DMA_SendSdramToLocal(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          SourceAddress,
                         const UWORD32          DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_SDRAM_SOURCE_PORT, SourceAddress);
 DMA_SetDestAddress(ChannelId, DMA_LOCAL_IMIF_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_SDRAM_SOURCE_PORT,
            DMA_LOCAL_IMIF_DESTINATION_PORT,
            /* all access to SDRAM/EMIF/LOCAL ports in 32 bits */
            DMA_32BITS_TRANSFER_WIDTH,
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}

/*
---------------------------------------------------------------------------
               DMA_SendLocalToSdram                                       -
---------------------------------------------------------------------------
*/
void DMA_SendLocalToSdram(const DMA_ChannelId_t     ChannelId,
                         const DMA_Priority_t      Priority,
                         const UWORD32          SourceAddress,
                         const UWORD32          DestinationAddress,
                         const UWORD16             TransferLength,
                         const DMA_Autoinit_t      AutoInitToggle,
                         const DMA_HalfBlockTrIE_t HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_LOCAL_IMIF_SOURCE_PORT, SourceAddress);
 DMA_SetDestAddress(ChannelId, DMA_SDRAM_DESTINATION_PORT, DestinationAddress);

 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_LOCAL_IMIF_SOURCE_PORT,
            DMA_SDRAM_DESTINATION_PORT,
            /* all access to SDRAM/EMIF/LOCAL ports in 32 bits */
            DMA_32BITS_TRANSFER_WIDTH,
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            DMA_CHANNEL_ACTIVE,
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE,
            DMA_ENABLE_DROP_IT);

  /* Goback to user mode after commit update of Registers */
  
}




/*
---------------------------------------------------------------------------
               DMA_BlockTransferCompleted                                 -
---------------------------------------------------------------------------
*/
boolean_t DMA_BlockTransferCompleted(const DMA_ChannelId_t ChannelId)
{
boolean_t BlockCompleted;

  UWORD32 MemReg; 
  MemReg = *(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr;

  BlockCompleted = (boolean_t)((MemReg & DMA_BLOCK_TR_COND_MSK) 
                    >> DMA_BLOCK_TR_COND_BITPOS);

  /* clear the condition bit after reading */
  MemReg &= ~DMA_BLOCK_TR_COND_MSK;
  /* Update the DMA channel control register */
  *(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr = MemReg;

  return ( BlockCompleted );
}



void DMA_DisableAutoinitMode(const DMA_ChannelId_t ChannelId)
{
UWORD32 value;

  /* extract all the fields but Priority */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_PRIO_MSK;
  // Clear autoinit bit
  value &= ~DMA_AUTOINIT_MSK;
  // 
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}

/*
-----------------------------------------------------------------------
               DMA_SetControlReg                                      -
-----------------------------------------------------------------------