dma.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

*/
boolean_t DMA_IsChannelEnable(const DMA_ChannelId_t ChannelId)
{
return ((boolean_t)(*(UWORD32*)RegisterAddrUsr[ChannelId].dma_ccr 
         & DMA_ENABLE_CHANNEL_MSK) );
}

/*
---------------------------------------------------------------------------
               DMA_SendRheaToRhea                                         -
---------------------------------------------------------------------------
*/
void DMA_SendRheaToRhea
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD16                  SrceRheaOffset,
        const RHEA_Strobe0ChipSelect_t SrceRheaChipSelect,
        const UWORD16                  DestRheaOffset,
        const RHEA_Strobe0ChipSelect_t DestRheaChipSelect,
        const UWORD16                  TransferLength,
		  const RHEA_Access_Size_t			MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetRheaSourceAddress(ChannelId, SrceRheaOffset, SrceRheaChipSelect);
 DMA_SetRheaDestAddress(ChannelId, DestRheaOffset, DestRheaChipSelect);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_RHEA_SOURCE_PORT,
            DMA_RHEA_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */

  
}

/*
---------------------------------------------------------------------------
               DMA_SendEmifToRhea                                         -
---------------------------------------------------------------------------
*/
void DMA_SendEmifToRhea
       (const DMA_ChannelId_t		ChannelId,
        const DMA_Priority_t		Priority,
        const UWORD32			SourceAddress,
        const UWORD16			DestRheaOffset,
        const RHEA_Strobe0ChipSelect_t	DestRheaChipSelect,
        const UWORD16			TransferLength,
        const RHEA_Access_Size_t	MemoryRheaWidth,
        const DMA_Autoinit_t		AutoInitToggle,
        const DMA_HalfBlockTrIE_t	HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_EMIF_SOURCE_PORT, SourceAddress);
 DMA_SetRheaDestAddress(ChannelId, DestRheaOffset, DestRheaChipSelect);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_EMIF_SOURCE_PORT,
            DMA_RHEA_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */

  
}
/*
---------------------------------------------------------------------------
               DMA_SendRheaToEmif                                         -
---------------------------------------------------------------------------
*/
void DMA_SendRheaToEmif
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD16               	SrceRheaAddr,
        const RHEA_Strobe0ChipSelect_t SrceRheaChipSelect,
        const UWORD32               	DestinationAddress,
        const UWORD16                  TransferLength,
		  const RHEA_Access_Size_t			MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);

 DMA_SetRheaSourceAddress(ChannelId, SrceRheaAddr, SrceRheaChipSelect);
 DMA_SetDestAddress(ChannelId, DMA_EMIF_DESTINATION_PORT, DestinationAddress);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_RHEA_SOURCE_PORT,
            DMA_EMIF_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */
 
}

/*
---------------------------------------------------------------------------
               DMA_SendEmifToRhea                                         -
---------------------------------------------------------------------------
*/
void DMA_SendImifLbToRhea
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD32               SourceAddress,
        const UWORD16               DestRheaOffset,
        const RHEA_Strobe0ChipSelect_t DestRheaChipSelect,
        const UWORD16                  TransferLength,
		  const RHEA_Access_Size_t			MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_LOCAL_IMIF_SOURCE_PORT, SourceAddress);
 DMA_SetRheaDestAddress(ChannelId, DestRheaOffset, DestRheaChipSelect);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_LOCAL_IMIF_SOURCE_PORT,
            DMA_RHEA_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */

  
}
/*
---------------------------------------------------------------------------
               DMA_SendRheaToImifLb                                         -
---------------------------------------------------------------------------
*/
void DMA_SendRheaToImifLb
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD16               	SrceRheaAddr,
        const RHEA_Strobe0ChipSelect_t SrceRheaChipSelect,
        const UWORD32               	DestinationAddress,
        const UWORD16                  TransferLength,
		  const RHEA_Access_Size_t			MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);

 DMA_SetRheaSourceAddress(ChannelId, SrceRheaAddr, SrceRheaChipSelect);
 DMA_SetDestAddress(ChannelId, DMA_LOCAL_IMIF_DESTINATION_PORT, DestinationAddress);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_RHEA_SOURCE_PORT,
            DMA_LOCAL_IMIF_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */
 
}


/*
---------------------------------------------------------------------------
               DMA_SendSdramToRhea                                         -
---------------------------------------------------------------------------
*/
void DMA_SendSdramToRhea
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD32               	SourceAddress,
        const UWORD16               	DestRheaOffset,
        const RHEA_Strobe0ChipSelect_t DestRheaChipSelect,
        const UWORD16                  TransferLength,
		  const RHEA_Access_Size_t			MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_SDRAM_SOURCE_PORT, SourceAddress);
 DMA_SetRheaDestAddress(ChannelId, DestRheaOffset, DestRheaChipSelect);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_SDRAM_SOURCE_PORT,
            DMA_RHEA_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */

  
}


/*
---------------------------------------------------------------------------
               DMA_SendRheaToSdram                                        -
---------------------------------------------------------------------------
*/
void DMA_SendRheaToSdram
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD16                  SrceRheaAddr,
        const RHEA_Strobe0ChipSelect_t SrceRheaChipSelect,
        const UWORD32                  DestinationAddress,
        const UWORD16                  TransferLength,
	const RHEA_Access_Size_t       MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);

 DMA_SetRheaSourceAddress(ChannelId, SrceRheaAddr, SrceRheaChipSelect);
 DMA_SetDestAddress(ChannelId, DMA_SDRAM_DESTINATION_PORT, DestinationAddress);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_RHEA_SOURCE_PORT,
            DMA_SDRAM_DESTINATION_PORT,
            (DMA_TransferWidth_t)MemoryRheaWidth, /* used only with rhea port */
            DMA_SOURCE_ADDRESS_MODE_INCREMENT,
            DMA_DESTINATION_ADDRESS_MODE_INCREMENT,
            AutoInitToggle,
            DMA_NOT_SYNCHRONISED, /* Transfer initiated by Enable bit */
            /* Initiate DMA Transfer on Hard peripheral request for synchronous transfer*/
            DMA_CHANNEL_ACTIVE,   /* Enable Bit */
            DMA_ENABLE_TIMEOUT_BUSERROR_IT,
            DMA_ENABLE_BLOCK_TRANSFER_IT,
            HalfBlockIE, /* Enable or not the Half block Interrupt */
            DMA_ENABLE_DROP_IT); /* Idem for drop IT */
 
}

/*
---------------------------------------------------------------------------
               DMA_ConfigureSdramToRhea                                   -
---------------------------------------------------------------------------
*/
void DMA_ConfigureSdramToRhea
       (const DMA_ChannelId_t          ChannelId,
        const DMA_Priority_t           Priority,
        const UWORD32               	SourceAddress,
        const RHEA_Strobe0ChipSelect_t DestRheaChipSelect,
        const UWORD16               	DestRheaOffset,
        const UWORD16                  TransferLength,
	const RHEA_Access_Size_t       MemoryRheaWidth,
        const DMA_Autoinit_t           AutoInitToggle,
        const DMA_HalfBlockTrIE_t      HalfBlockIE)
{ 
 DMA_SetBlockCount(ChannelId, TransferLength);
 DMA_SetSourceAddress(ChannelId, DMA_SDRAM_SOURCE_PORT, SourceAddress);
 DMA_SetRheaDestAddress(ChannelId, DestRheaOffset, DestRheaChipSelect);


 DMA_SetControlReg
           (ChannelId,
            Priority,
            DMA_SDRAM_SOURCE_PORT,
            DMA_RHEA_DESTINATION_PORT,