dma.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename       	: DMA.c

   Description    	: Body file for the SatuStar DMA Controller

   Project        	: Satustar

   Author         	: Francois Reygagne [e-mail]


===============================================================================
*/

#include "dma.h"
#include "mem.h"


/*
-----------------------------------------------------
  DMA  REGISTERS  MAPPING ADDRESS                   -
-----------------------------------------------------
*/
/*DMA  CHANNEL CONTROL  REGISTERS  MAPPING ADDRESS */
#define DMA_REG_CCR_OFFSET     (UWORD32)0x00
#define DMA_REG_SRC_ADD_OFFSET 0x04
#define DMA_REG_DST_ADD_OFFSET 0x08
#define DMA_REG_BKC_OFFSET     0x0C

/*DMA CHANNEL LCD REGISTER MAPPING ADDRESS */
#define DMA_REG_LCD_CTROL_OFFSET      0x40
#define DMA_REG_LCD_TOP_FRAME1_OFFSET 0x44
#define DMA_REG_LCD_BOT_FRAME1_OFFSET 0x48
#define DMA_REG_LCD_TOP_FRAME2_OFFSET 0x4C
#define DMA_REG_LCD_BOT_FRAME2_OFFSET 0x50
#define DMA_REG_LCD_READ_ADD_PTR_OFFSET 0x54
/* FIFOS REGISTER MAPPING ADDRESS */
#define DMA_REG_FIFOS_OFFSET          0x60

#define DMA_REG_LCD_CTROL_SUPERVISOR_ADDR      \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_CTROL_OFFSET)

#define DMA_REG_LCD_TOP_FRAME1_SUPERVISOR_ADDR \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_TOP_FRAME1_OFFSET)

#define DMA_REG_LCD_BOT_FRAME1_SUPERVISOR_ADDR \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_BOT_FRAME1_OFFSET)

#define DMA_REG_LCD_TOP_FRAME2_SUPERVISOR_ADDR \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_TOP_FRAME2_OFFSET)

#define DMA_REG_LCD_BOT_FRAME2_SUPERVISOR_ADDR \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_BOT_FRAME2_OFFSET)

#define DMA_REG_LCD_READ_ADD_PTR_SUPERVISOR_ADDR \
        (MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + DMA_REG_LCD_READ_ADD_PTR_OFFSET)


/*
----------------------------------------------------------
  DMA  CHANNEL  CONTROL  REGISTER  MASK AND BIT POSITION -
----------------------------------------------------------
*/
#define DMA_CHANNEL_CTROL_REG_RESET_VALUE 0x00000000
#define DMA_CHANNEL_CTROL_REG_MSK 			0x1fffff
#define DMA_PRIO_MSK            0x00000001  /* Channel Priority Mask */
#define DMA_SRC_PORT_MSK        0x00000006  /* Source Address Port Mask */
#define DMA_DST_PORT_MSK        0x00000018  /* Destination Address Port Mask */
/* transfert width mask used only for Rhea Port */
#define DMA_TRANSFERT_WIDTH_MSK 0x00000060 

#define DMA_SRC_ADDR_MODE_MSK   0x00000080 /* Source Address Mode Mask */
#define DMA_DST_ADDR_MODE_MSK   0x00000100 /* Destination Address Mode Mask */
#define DMA_AUTOINIT_MSK        0x00000200 /* Autoinitialization Mode Mask */
#define DMA_SYNCHRO_MSK         0x00000400 /* Synchronisation Mode Mask */
#define DMA_ENABLE_CHANNEL_MSK  0x00000800 /* Channel Enable Mask */

/* Condition Bit Fields notifying significant DMA events/problems */
#define DMA_BUS_ERROR_IE_MSK    0x00001000 /* TimeOut/BusError Enable Mask */
#define DMA_BLOCK_TR_IE_MSK     0x00002000 
#define DMA_HALF_BK_IE_MSK      0x00004000 
#define DMA_DROP_IE_MSK         0x00008000 
#define DMA_BUS_ERROR_COND_MSK  0x00010000 
#define DMA_BLOCK_TR_COND_MSK   0x00020000
#define DMA_HALF_BK_COND_MSK    0x00040000
#define DMA_DROP_COND_MSK       0x00080000
#define DMA_CLEAR_ALL_CONDBITS  0x01F0FFFF
#define DMA_FIFO_BYTES_LEFT_MSK 0x00F00000
#define DMA_FIFO_STATUS_MSK     0x01000000


#define DMA_PRIO_BITPOS             0  
#define DMA_SRC_PORT_BITPOS         1  
#define DMA_DST_PORT_BITPOS         3 
#define DMA_TRANSFERT_WIDTH_BITPOS  5
#define DMA_SRC_ADDR_MODE_BITPOS    7 
#define DMA_DST_ADDR_MODE_BITPOS    8 
#define DMA_AUTOINIT_BITPOS         9 
#define DMA_SYNCHRO_BITPOS         10
#define DMA_ENABLE_CHANNEL_BITPOS  11
#define DMA_BUS_ERROR_IE_BITPOS    12
#define DMA_BLOCK_TR_IE_BITPOS     13
#define DMA_HALF_BK_IE_BITPOS      14
#define DMA_DROP_IE_BITPOS         15
#define DMA_BUS_ERROR_COND_BITPOS  16
#define DMA_BLOCK_TR_COND_BITPOS   17
#define DMA_HALF_BK_COND_BITPOS    18
#define DMA_DROP_COND_BITPOS       19
#define DMA_FIFO_BYTES_LEFT_BITPOS 20
#define DMA_FIFO_STATUS_BITPOS     24

 
/*
----------------------------------------------------
  DMA  SOURCE/DESTINATION ADDRESS  REGISTER        -
----------------------------------------------------
*/
#define DMA_SOURCE_DESTINATION_ADDR_REG_RESET_VALUE 0x00000000
#define DMA_SOURCE_DESTINATION_ADDR_MSK 0x7FFFFFFF
#define DMA_SRC_DST_SDRAM_ADDR_MSK 0x03FFFFFF  /* SDRAM port address Mask */
#define DMA_SRC_DST_EMIF_ADDR_MSK  0x03FFFFFF  /* EMIF port address Mask */
#define DMA_SRC_DST_LOCAL_ADDR_MSK 0x7FFFFFFF  /* LOCAL port Mask */
#define DMA_SRC_DST_RHEA_ADDR_MSK  0x000007FF  /* RHEA port address Mask */
#define DMA_SRC_DST_RHEA_CS_MSK    0x001F0000  /* SDRAM port chip select Mask */

#define DMA_SRC_DST_SDRAM_ADDR_BITPOS   0
#define DMA_SRC_DST_EMIF_ADDR_BITPOS    0
#define DMA_SRC_DST_LOCAL_ADDR_BITPOS   0
#define DMA_SRC_DST_RHEA_ADDR_BITPOS    0
#define DMA_SRC_DST_RHEA_CS_BITPOS     16

/*
--------------------------------------------------------------------------------------
  DMA BLOCK COUNT REGISTER Contains                                                  -
  -the number of word to transfer (16 first bits) and                                -
  -the next following address of the last data written on destination (16 last bits) -
   used to indicate the next position in the memory mapping where the next data      -
   could be written.                                                                 -
--------------------------------------------------------------------------------------
*/
#define DMA_BLK_COUNT_REG_RESET_VALUE 0x00000000
#define DMA_BLK_COUNT_MSK             0x0000FFFF
#define DMA_NEXT_WRITE_ADD_MSK        0xFFFF0000
#define DMA_BLK_COUNT_BITPOS          0
#define DMA_NEXT_WRITE_ADD_BITPOS     16


/*
----------------------------------------------------------
  DMA LCD CONTROL REGISTER                               -
----------------------------------------------------------
*/
#define DMA_LCD_CTRL_REG_RESET_VALUE       0x00000000
#define DMA_LCD_CTRL_MSK        				 0x0000003F
#define DMA_LCD_CTRL_FRAME_MODE_MSK        0x00000001
#define DMA_LCD_CTRL_FRAME_IT_IE_MSK       0x00000002
#define DMA_LCD_CTRL_BUS_ERROR_IE_MSK      0x00000004
#define DMA_LCD_CTRL_FRAME1_IT_COND_MSK    0x00000008
#define DMA_LCD_CTRL_FRAME2_IT_COND_MSK    0x00000010
#define DMA_LCD_CTRL_BUS_ERROR_IT_COND_MSK 0x00000020

#define DMA_LCD_CTRL_FRAME_MODE_BITPOS        0
#define DMA_LCD_CTRL_FRAME_IT_IE_BITPOS       1
#define DMA_LCD_CTRL_BUS_ERROR_IE_BITPOS      2
#define DMA_LCD_CTRL_FRAME1_IT_COND_BITPOS    3
#define DMA_LCD_CTRL_FRAME2_IT_COND_BITPOS    4
#define DMA_LCD_CTRL_BUS_ERROR_IT_COND_BITPOS 5

/*
----------------------------------------------------------
  DMA LCD TOP BOT ADDRESS  REGISTER                      -
----------------------------------------------------------
*/
#define DMA_LCD_TOP_BOT_RESET_VALUE  0x00000000
// 26 bits length register, multiple of 32 =>bit 0->Bit 4 =0
#define DMA_LCD_TOP_FRAME_MSK    0x03FFFFE0 

// 26 bits length register, multiple of 2 =>bit 0 =0
#define DMA_LCD_BOT_FRAME_MSK    0x03FFFFFE 

/*
----------------------------------------------------------
  DMA FIFOS REGISTER                                     -
----------------------------------------------------------
*/
#define DMA_FIFOS_RESET_VALUE 0x00000000
#define DMA_FIFOS_MSK         0xFFFFFFFF

/*
-------------------------------
  DMA_RegisterMapping_t       -
-------------------------------
*/
typedef struct {
  UWORD32 dma_ccr;
  UWORD32 dma_src_add;
  UWORD32 dma_dst_add;
  UWORD32 dma_bkc;
} DMA_RegisterMapping_t;

/*
----------------------------------
  DMA_ReadOnlyRegisterMapping_t  -
----------------------------------
*/
typedef struct {
  UWORD32 dma_ccr;
  UWORD32 dma_src_add;
  UWORD32 dma_dst_add;
  UWORD32 dma_bkc;
  UWORD32 dma_fifo;
} DMA_ReadRegisterMapping_t;


typedef DMA_RegisterMapping_t     RegisterAddr_t     [ DMA_NUMBER_OF_CHANNEL ] ; 
typedef DMA_ReadRegisterMapping_t ReadRegisterAddr_t [ DMA_NUMBER_OF_CHANNEL ] ; 


/* Table giving the Register Address per each channel Supervisor mode */
static const RegisterAddr_t  RegisterAddrSup 
  = { 
      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR},

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 0x10},

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 2 * 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 2 * 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 2 * 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 2 * 0x10},

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 3 * 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 3 * 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 3 * 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_SUPERVISOR_ADDR + 3 * 0x10}, 
    };

/* Table giving the Register Address per each channel Supervisor mode */
static const ReadRegisterAddr_t  RegisterAddrUsr 
  = { 
      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR,
        DMA_REG_FIFOS_OFFSET   + MEM_DMA_CONTROLLER_USER_ADDR}, /*Read Only*/

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 0x10,
        DMA_REG_FIFOS_OFFSET   + MEM_DMA_CONTROLLER_USER_ADDR + 0x04 },

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 2 * 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 2 * 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 2 * 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 2 * 0x10,
        DMA_REG_FIFOS_OFFSET   + MEM_DMA_CONTROLLER_USER_ADDR + 2 * 0x04 },

      { DMA_REG_CCR_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 3 * 0x10, 
        DMA_REG_SRC_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 3 * 0x10,
        DMA_REG_DST_ADD_OFFSET + MEM_DMA_CONTROLLER_USER_ADDR + 3 * 0x10,
        DMA_REG_BKC_OFFSET     + MEM_DMA_CONTROLLER_USER_ADDR + 3 * 0x10,
        DMA_REG_FIFOS_OFFSET   + MEM_DMA_CONTROLLER_USER_ADDR + 3 * 0x04 }    
    };


/*
---------------------------------------------------------------------
               DMA_EnableChannel                                    -
---------------------------------------------------------------------
*/
void DMA_EnableChannel(const DMA_ChannelId_t ChannelId)
{
UWORD32 value;

  /* extract all the fields but bit Enable channel */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_ENABLE_CHANNEL_MSK;
  /* Disable the channel  */
  value |= (DMA_CHANNEL_ACTIVE << DMA_ENABLE_CHANNEL_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}

/*
---------------------------------------------------------------------
 NAME        : DMA_DisableChannel                                   -
---------------------------------------------------------------------
*/
void DMA_DisableChannel(const DMA_ChannelId_t ChannelId)
{
UWORD32 value;

  /* extract all the fields but bit Enable channel */
  value = *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr & ~DMA_ENABLE_CHANNEL_MSK;
  /* Disable the channel  */
  value |= (DMA_CHANNEL_DISABLE << DMA_ENABLE_CHANNEL_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)RegisterAddrSup[ChannelId].dma_ccr = value;
}


/*
----------------------------------------------------------------------
               DMA_IsChannelEnable                                   -
----------------------------------------------------------------------