📄 neptune_fpga.c
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//========================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reprofuction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work
// Created 2000, (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
// Filename :neptune_fpga.c
//
// Date of Module Modification:11/19/04
// Date of Generation :11/20/04
//
//
//========================================================================
#include "global_types.h"
#include "neptune_fpga.h"
#include "mapping.h"
void FPGA_EnableUARTshdn(void)
{
FPGA_HANDSET_UART_SHUTDOWN_REG = 0x0;
}
void FPGA_EnableUART1(void)
{
FPGA_UART1_REG = 0x2;
//PALADIUM_CPLD_UART3_DOLO_OR_LOOPBACK_ADDR = 0x1;
}
void FPGA_EnableUART2(void)
{
FPGA_UART1_REG = 0x3;
}
void FPGA_EnableUART3(void)
{
FPGA_UART1_REG = 0x4;
}
void FPGA_readtestreg(void)
{
if ((UWORD8)FPGA_TEST_REG != 0xAA)
printf("Warning ! ---- Failed reading FPGA\n");
}
UWORD8 FPGA_readversion(void)
{
return FPGA_REV_REG;
}
UWORD8 FPGA_cpldreadversion(void)
{
return FPGA_CPLD_REV_REG;
}
void FPGA_EnableUWIREcs0(void)
{
FPGA_SPI_REG = 0x7;
}
void FPGA_EnableUWIREcs3(void)
{
FPGA_SPI_REG = 0x8;
}
void FPGA_readtest(void)
{
}
void FPGA_setloopback(void)
{
}
void FPGA_Loop_Back_McBSP1_DX_2_DR(void){
FPGA_MCBSP1_REG = 0x1;
}
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