ulpd.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  case MMC: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MMC_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MMC_REQ_NUMB, 1);	         
     break;	
    }          

  case MMC2: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MMC2_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MMC2_REQ_NUMB, 1);	         
     break;	
    }          
           
  case UWIRE: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UWIRE_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UWIRE_REQ_NUMB, 1);	         
     break;	
    }           
 
  case IO: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_IO_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_IO_REQ_NUMB, 1);	         
     break;	
    }      
           
  }              
}



//---------------------------------------------------------------------
// NAME        : ULPD_SoftReqEnable
//
// DESCRIPTION : Enable SOFT REQ Register
//
// PARAMETERS  : 	DPLL	  	or       
//             		CAMERA		or       
//		        MCSI		or       
//	      		USB_PVCI	or
//	      		USB_TG		or       
//             		UART1		or       
//             		UART2		or                            
//	      		UART3		or       
//	      		MMC		or       
//	      		MMC2		or       
//             		UWIRE		or                
//             		IO		       
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_SoftReqDisable(ULPD_SoftReq_t SoftReq)
{
 switch (SoftReq)
 {
  case DPLL: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_NUMB, 0);	         
     break;	
    }
  
  case CAMERA: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_CAMERA_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_CAMERA_REQ_NUMB, 0);	         
     break;	
    }       
  
  case MCSI: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MCSI_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MCSI_REQ_NUMB, 0);	         
     break;	
    }       

  case USB_PVCI: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_USB_PVCI_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_USB_PVCI_REQ_NUMB, 0);	         
     break;	
    }           
  
  case USB_OTG: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_USB_OTG_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_USB_OTG_REQ_NUMB, 0);	         
     break;	
    }           
  
  case UART1: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART1_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART1_REQ_NUMB, 0);	         
     break;	
    } 
    
  case UART2: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART2_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART2_REQ_NUMB, 0);	         
     break;	
    }          
             
  case UART3: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART3_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART3_REQ_NUMB, 0);	         
     break;	
    }          

  case MMC: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MMC_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MMC_REQ_NUMB, 0);	         
     break;	
    }          

  case MMC2: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MMC2_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MMC2_REQ_NUMB, 0);	         
     break;	
    }          
           
  case UWIRE: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UWIRE_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UWIRE_REQ_NUMB, 0);	         
     break;	
    }           
 
  case IO: 
    {
     SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_IO_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_IO_REQ_NUMB, 0);	         
     break;	
    }      
           
  }              
}



//---------------------------------------------------------------------
// NAME        : ULPD_ConfigureChipIdle
//
// DESCRIPTION : Configure Chip Ilde
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------

void ULPD_ConfigureChipIdle() {
  
  // Set all MPU domain clocks to go off when the MPU goes idle
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLTIM_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLDPLL_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLIF_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLPER_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLXORP_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDLWDT_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_IDL_CLKOUT_ARM_POS);

  // Set OMAP3.2 wakeup mode: on interrupt event and idle acknowledge from ULPD
  ClearBitIndex(CLKRST_ARM_IDLECT1, CLKRST_ARM_IDLECT1_WKUP_MODE_POS);

  // Configure NEPTUNE to disable idle control for RNG module (don't wait for idleack from RNG)
  ClearBitIndex(CONFIGURATION_RESET_CONTROL, CONFIGURATION_RESET_CONTROL_CONF_RNG_IDLE_MODE_POS);

  // Set idle entry for TC clocks.
  SetBitIndex(CLKRST_ARM_IDLECT3, CLKRST_ARM_IDLECT3_IDLOCPI_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT3, CLKRST_ARM_IDLECT3_IDLTC1_ARM_POS);
  SetBitIndex(CLKRST_ARM_IDLECT3, CLKRST_ARM_IDLECT3_IDLTC2_ARM_POS);

  // Switch off the OCPI clock
  ClearBitIndex(CLKRST_ARM_IDLECT3, CLKRST_ARM_IDLECT3_EN_OCPI_CK_POS);

  // Enable EMIFS power down
  SetBitIndex(EMIFS_EMIFS_CONFIG, EMIFS_EMIFS_CONFIG_PDE_POS);
  SetBitIndex(EMIFS_EMIFS_CONFIG, EMIFS_EMIFS_CONFIG_PWD_EN_POS);

  // Disable MGS3
  ClearBitIndex(CLKRST_ARM_CKCTL, CLKRST_ARM_CKCTL_EN_DSPCK_POS);

  // Enable SDRAM self refresh mode
  SetBitIndex(EMIFF_EMIFF_SDRAM_CONFIG, EMIFF_EMIFF_SDRAM_CONFIG_SLRF_POS);

  // Enable SDRAM power dowm
  SetBitIndex(EMIFF_EMIFF_SDRAM_CONFIG, EMIFF_EMIFF_SDRAM_CONFIG_PWD_POS);

  // Disable SDRAM clock
  SetBitIndex(EMIFF_EMIFF_SDRAM_CONFIG, EMIFF_EMIFF_SDRAM_CONFIG_CLK_POS);
  
  // Clear the Self refresh while in standby time
  ClearBitIndex(EMIFF_EMIFF_CONFIG_REG2, EMIFF_EMIFF_CONFIG_REG2_SLFR_STBY_POS);

  // Switch off ARM API, GPIO, LCD clocks
  ClearBitIndex(CLKRST_ARM_IDLECT2, CLKRST_ARM_IDLECT2_EN_APICK_POS);
  ClearBitIndex(CLKRST_ARM_IDLECT2, CLKRST_ARM_IDLECT2_EN_GPIOCK_POS);
  ClearBitIndex(CLKRST_ARM_IDLECT2, CLKRST_ARM_IDLECT2_EN_LCDCK_POS);

  // Disable the Watch Dog timer function.
  TIME_WdgDisable();

}



//---------------------------------------------------------------------
// NAME        : ULPD_ConfigureDeepSleep
//
// DESCRIPTION : Configure Deep Sleep Mode
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_ConfigureDeepSleep() {

  // Prepare for OMAP3.2 to enter chip idle mode
  ULPD_ConfigureChipIdle();

  // Configure ULPD to disable USB PVCI clock
  SetBitIndex(ULPD_SOFT_DISABLE_REQ_REG, ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_PVCI_REQ_POS);
  SetBitIndex(ULPD_SOFT_DISABLE_REQ_REG, ULPD_SOFT_DISABLE_REQ_REG_DIS_USB_OTG_REQ_POS);
  
  // ED: Disable hardware signal
  //SetBitIndex(ULPD_SOFT_DISABLE_REQ_REG, ULPD_SOFT_DISABLE_REQ_REG_DIS_CLK_IO_REQ_POS);

  // Configure ULPD to set the voltage setup timer to 2 sleep clock cycles (delay when going out of deep sleep)
  SetGroupBits(ULPD_SETUP_26M_REG,
               ULPD_SETUP_26M_REG_SETUP_26M_POS,
               ULPD_SETUP_26M_REG_SETUP_26M_NUMB,
               0x2);
}

//---------------------------------------------------------------------
// NAME        : ULPD_ConfigureDeepSleepUsb
//
// DESCRIPTION : Configure Deep Sleep Mode
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_ConfigureDeepSleepUsb() {

// disable the usb otg hw requests to ulpd
  SetBitIndex(USB_OTG_CTRL_OTG_SYSCON_1_32, USB_OTG_CTRL_OTG_SYSCON_1_32_OTG_IDLE_EN_POS);
  SetBitIndex(USB_OTG_CTRL_OTG_SYSCON_1_32, USB_OTG_CTRL_OTG_SYSCON_1_32_HST_IDLE_EN_POS);
  SetBitIndex(USB_OTG_CTRL_OTG_SYSCON_1_32, USB_OTG_CTRL_OTG_SYSCON_1_32_DEV_IDLE_EN_POS);

  ClearBitIndex(USB_OTG_CTRL_OTG_SYSCON_2_32, USB_OTG_CTRL_OTG_SYSCON_2_32_OTG_EN_POS);
  ClearBitIndex(USB_OTG_CTRL_OTG_SYSCON_2_32, USB_OTG_CTRL_OTG_SYSCON_2_32_UHOST_EN_POS);

  SetGroupBits(USB_OTG_CTRL_OTG_SYSCON_2_32,
	       USB_OTG_CTRL_OTG_SYSCON_2_32_HMC_MODE_POS,
	       USB_OTG_CTRL_OTG_SYSCON_2_32_HMC_MODE_NUMB,
	       0x16);
  
  ULPD_ConfigureChipIdle();
 
  // Configure ULPD to set the voltage setup timer to 2 sleep clock cycles (delay when going out of deep sleep)
  SetGroupBits(ULPD_SETUP_26M_REG,
               ULPD_SETUP_26M_REG_SETUP_26M_POS,
               ULPD_SETUP_26M_REG_SETUP_26M_NUMB,
               0x2);
}

//---------------------------------------------------------------------
// NAME        : ULPD_GsmClockEn
//
// DESCRIPTION : Enable the GSM clocks (13 and 26 MHz)
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_GsmClockEn(void)
{
 ULPD_CLOCK_GSM_REG = 0x1;
}

//---------------------------------------------------------------------
// NAME        : ULPD_GsmClockDis
//
// DESCRIPTION : Disable the GSM clocks (13 and 26 MHz)
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_GsmClockDis(void)
{
 ULPD_CLOCK_GSM_REG = 0x0;
}