📄 ulpd.c
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END_RW_TEST();
BEGIN_RW_TEST(ULPD_SETUP_VTCXO_REG,16);
RW_PREPARE_WRITE(ULPD_SETUP_VTCXO_REG,SETUP_VTCXO,16);
RW_WRITE(ULPD_SETUP_VTCXO_REG);
RW_TEST_READ(ULPD_SETUP_VTCXO_REG,SETUP_VTCXO,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_SETUP_VTCXO_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_CLOCK_CTRL_REG,16);
RW_PREPARE_WRITE(ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
RW_WRITE(ULPD_CLOCK_CTRL_REG);
RW_TEST_READ(ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_CLOCK_CTRL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_SOFT_REQ_REG,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_IO_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_UWIRE_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_MMC2_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_MMC_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_UART3_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_UART2_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_UART1_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_USB_OTG_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_USB_PVCI_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_MCSI_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_CAMERA_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
RW_WRITE(ULPD_SOFT_REQ_REG);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_IO_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_UWIRE_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_MMC2_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_MMC_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_UART3_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_UART2_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_UART1_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_USB_OTG_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_USB_PVCI_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_MCSI_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_CAMERA_REQ,16);
RW_TEST_READ(ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_SOFT_REQ_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_APLL_CTRL_STATUS,16);
//ULPD_APLL_CTRL_STATUS,LOCK_STATUS is Read Only
RW_PREPARE_WRITE(ULPD_APLL_CTRL_STATUS,PLL_CTRL_RES,16);
RW_PREPARE_WRITE(ULPD_APLL_CTRL_STATUS,PLL_CONTROL,16);
RW_WRITE(ULPD_APLL_CTRL_STATUS);
//ULPD_APLL_CTRL_STATUS,LOCK_STATUS is Read Only
RW_TEST_READ(ULPD_APLL_CTRL_STATUS,PLL_CTRL_RES,16);
RW_TEST_READ(ULPD_APLL_CTRL_STATUS,PLL_CONTROL,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_APLL_CTRL_STATUS);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_POWER_CTRL_REG,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,DISABLE_RF_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,ENABLE_RF_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,VMODE_CONTROL,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,SOFT_LDO_SLEEP,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
//ULPD_POWER_CTRL_REG,LDO_STEADY is Read Only
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,POWERSEL_SLICER,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,VMODE_CTRL_DYNAMIC_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,DIS_HW_RF_BG_EN,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
RW_PREPARE_WRITE(ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
RW_WRITE(ULPD_POWER_CTRL_REG);
RW_TEST_READ(ULPD_POWER_CTRL_REG,DISABLE_RF_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,ENABLE_RF_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,VMODE_CONTROL,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,SOFT_LDO_SLEEP,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
//ULPD_POWER_CTRL_REG,LDO_STEADY is Read Only
RW_TEST_READ(ULPD_POWER_CTRL_REG,POWERSEL_SLICER,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,VMODE_CTRL_DYNAMIC_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,DIS_HW_RF_BG_EN,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
RW_TEST_READ(ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_POWER_CTRL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_SETUP_RF_REG,16);
RW_PREPARE_WRITE(ULPD_SETUP_RF_REG,SETUP_RF,16);
RW_WRITE(ULPD_SETUP_RF_REG);
RW_TEST_READ(ULPD_SETUP_RF_REG,SETUP_RF,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_SETUP_RF_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_SOFT_DISABLE_REQ_REG,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_CAMERA_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_PVCI_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_OTG_REQ,16);
RW_PREPARE_WRITE(ULPD_SOFT_DISABLE_REQ_REG,DIS_CLK_IO_REQ,16);
RW_WRITE(ULPD_SOFT_DISABLE_REQ_REG);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_CAMERA_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_PVCI_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_OTG_REQ,16);
RW_TEST_READ(ULPD_SOFT_DISABLE_REQ_REG,DIS_CLK_IO_REQ,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_SOFT_DISABLE_REQ_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_RESET_STATUS,16);
RW_PREPARE_WRITE(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
RW_PREPARE_WRITE(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
RW_PREPARE_WRITE(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
RW_PREPARE_WRITE(ULPD_RESET_STATUS,POWER_ON_RESET,16);
RW_WRITE(ULPD_RESET_STATUS);
RW_TEST_READ(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
RW_TEST_READ(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
RW_TEST_READ(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
RW_TEST_READ(ULPD_RESET_STATUS,POWER_ON_RESET,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_RESET_STATUS);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_CLK_IO_CTRL_REG,16);
RW_PREPARE_WRITE(ULPD_CLK_IO_CTRL_REG,CLK_IO_26M_DIV2,16);
RW_PREPARE_WRITE(ULPD_CLK_IO_CTRL_REG,CLK_IO_INV,16);
RW_PREPARE_WRITE(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_SEL,16);
RW_PREPARE_WRITE(ULPD_CLK_IO_CTRL_REG,CLK_IO_CLK_SEL,16);
RW_PREPARE_WRITE(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_REQ,16);
RW_WRITE(ULPD_CLK_IO_CTRL_REG);
RW_TEST_READ(ULPD_CLK_IO_CTRL_REG,CLK_IO_26M_DIV2,16);
RW_TEST_READ(ULPD_CLK_IO_CTRL_REG,CLK_IO_INV,16);
RW_TEST_READ(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_SEL,16);
RW_TEST_READ(ULPD_CLK_IO_CTRL_REG,CLK_IO_CLK_SEL,16);
RW_TEST_READ(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_REQ,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_CLK_IO_CTRL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_ENA_MEMORY_RETENTION_REG,16);
RW_PREPARE_WRITE(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVDD,16);
RW_PREPARE_WRITE(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVSS,16);
RW_WRITE(ULPD_ENA_MEMORY_RETENTION_REG);
RW_TEST_READ(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVDD,16);
RW_TEST_READ(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVSS,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_ENA_MEMORY_RETENTION_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_INC_FRAC_REG,16);
RW_PREPARE_WRITE(ULPD_INC_FRAC_REG,INC_FRAC,16);
RW_WRITE(ULPD_INC_FRAC_REG);
RW_TEST_READ(ULPD_INC_FRAC_REG,INC_FRAC,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_INC_FRAC_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_INC_SIXTEENTH_REG,16);
RW_PREPARE_WRITE(ULPD_INC_SIXTEENTH_REG,INC_SIXTEENTH,16);
RW_WRITE(ULPD_INC_SIXTEENTH_REG);
RW_TEST_READ(ULPD_INC_SIXTEENTH_REG,INC_SIXTEENTH,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_INC_SIXTEENTH_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_SETUP_FRAME_REG,16);
RW_PREPARE_WRITE(ULPD_SETUP_FRAME_REG,SETUP_FRAME,16);
RW_WRITE(ULPD_SETUP_FRAME_REG);
RW_TEST_READ(ULPD_SETUP_FRAME_REG,SETUP_FRAME,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_SETUP_FRAME_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_GSM_TIMER_INIT_REG,16);
RW_PREPARE_WRITE(ULPD_GSM_TIMER_INIT_REG,TIMER_INIT,16);
RW_WRITE(ULPD_GSM_TIMER_INIT_REG);
RW_TEST_READ(ULPD_GSM_TIMER_INIT_REG,TIMER_INIT,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_GSM_TIMER_INIT_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_GSM_TIMER_IT_REG,16);
//ULPD_GSM_TIMER_IT_REG,IT_GSM_TIMER is Read Only
RW_WRITE(ULPD_GSM_TIMER_IT_REG);
//ULPD_GSM_TIMER_IT_REG,IT_GSM_TIMER is Read Only
RW_WRITE_PREVIOUS_VALUE(ULPD_GSM_TIMER_IT_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_GSM_TIMER_CTRL_REG,16);
RW_PREPARE_WRITE(ULPD_GSM_TIMER_CTRL_REG,FREEZE,16);
RW_PREPARE_WRITE(ULPD_GSM_TIMER_CTRL_REG,LOAD,16);
RW_WRITE(ULPD_GSM_TIMER_CTRL_REG);
RW_TEST_READ(ULPD_GSM_TIMER_CTRL_REG,FREEZE,16);
RW_TEST_READ(ULPD_GSM_TIMER_CTRL_REG,LOAD,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_GSM_TIMER_CTRL_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_CLOCK_GSM_REG,16);
RW_PREPARE_WRITE(ULPD_CLOCK_GSM_REG,CLOCK_GSM_EN,16);
RW_WRITE(ULPD_CLOCK_GSM_REG);
RW_TEST_READ(ULPD_CLOCK_GSM_REG,CLOCK_GSM_EN,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_CLOCK_GSM_REG);
END_RW_TEST();
BEGIN_RW_TEST(ULPD_CLOCK_26M_CTRL,16);
RW_PREPARE_WRITE(ULPD_CLOCK_26M_CTRL,DIV2_26M_EN,16);
RW_WRITE(ULPD_CLOCK_26M_CTRL);
RW_TEST_READ(ULPD_CLOCK_26M_CTRL,DIV2_26M_EN,16);
RW_WRITE_PREVIOUS_VALUE(ULPD_CLOCK_26M_CTRL);
END_RW_TEST();
END_ACCESS_MODULE();
}
//---------------------------------------------------------------------
// NAME : ULPD_SoftReqEnable
//
// DESCRIPTION : Enable SOFT REQ Register
//
// PARAMETERS : DPLL or
// CAMERA or
// MCSI or
// USB_PVCI or
// USB_TG or
// UART1 or
// UART2 or
// UART3 or
// MMC or
// MMC2 or
// UWIRE or
// IO
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_SoftReqEnable(ULPD_SoftReq_t SoftReq)
{
switch (SoftReq)
{
case DPLL:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_DPLL_REQ_NUMB, 1);
break;
}
case CAMERA:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_CAMERA_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_CAMERA_REQ_NUMB, 1);
break;
}
case MCSI:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_MCSI_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_MCSI_REQ_NUMB, 1);
break;
}
case USB_PVCI:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_USB_PVCI_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_USB_PVCI_REQ_NUMB, 1);
break;
}
case USB_OTG:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_USB_OTG_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_USB_OTG_REQ_NUMB, 1);
break;
}
case UART1:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART1_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART1_REQ_NUMB, 1);
break;
}
case UART2:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART2_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART2_REQ_NUMB, 1);
break;
}
case UART3:
{
SetGroupBits16(ULPD_SOFT_REQ_REG, ULPD_SOFT_REQ_REG_SOFT_UART3_REQ_POS, ULPD_SOFT_REQ_REG_SOFT_UART3_REQ_NUMB, 1);
break;
}
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