ulpd.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work.
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : ulpd.c
//
//===============================================================================

#include "test.h"
#include "global_types.h"
#include "result.h"
#include "intvecs.h"
#include "ulpd.h"
#include "reset.h"
#include "errorcodes.h"
#include "error.h"
#include "omap_32_clkrst.h"
#include "configuration.h"
#include "omap_32_emifs.h"
#include "omap_32_emiff.h"
#include "usb_otg_ctrl.h"


//---------------------------------------------------------------------
// NAME        : ULPD_TestResetValue
//
// DESCRIPTION : Test the reset values of ULPD registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(ULPD_COUNTER_32_LSB_REG,16);
    TEST_FIELD_RESET(ULPD_COUNTER_32_LSB_REG,COUNTER_SLEEP_CLK_LSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_COUNTER_32_MSB_REG,16);
    TEST_FIELD_RESET(ULPD_COUNTER_32_MSB_REG,RESERVED,16);
    TEST_FIELD_RESET(ULPD_COUNTER_32_MSB_REG,COUNTER_32_MSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_COUNTER_HIGH_FREQ_LSB_REG,16);
    TEST_FIELD_RESET(ULPD_COUNTER_HIGH_FREQ_LSB_REG,COUNTER_HIGH_FREQ_LSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_COUNTER_HIGH_FREQ_MSB_REG,16);
    TEST_FIELD_RESET(ULPD_COUNTER_HIGH_FREQ_MSB_REG,COUNTER_HIGH_FREQ_MSB,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_GAUGING_CTRL_REG,16);
    TEST_FIELD_RESET(ULPD_GAUGING_CTRL_REG,OMAP_DPLL_DIV2,16);
    TEST_FIELD_RESET(ULPD_GAUGING_CTRL_REG,GAUGING_TYPE,16);
    TEST_FIELD_RESET(ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    TEST_FIELD_RESET(ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_IT_STATUS_REG,16);
    TEST_FIELD_RESET(ULPD_IT_STATUS_REG,IT_WAKEUP_USB,16);
    TEST_FIELD_RESET(ULPD_IT_STATUS_REG,OVERFLOW_32,16);
    TEST_FIELD_RESET(ULPD_IT_STATUS_REG,OVERFLOW_HI_FREQ,16);
    TEST_FIELD_RESET(ULPD_IT_STATUS_REG,IT_GAUGING,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SETUP_26M_REG,16);
    TEST_FIELD_RESET(ULPD_SETUP_26M_REG,SETUP_26M,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SETUP_SLICER_REG,16);
    TEST_FIELD_RESET(ULPD_SETUP_SLICER_REG,SETUP_SLICER,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SETUP_VTCXO_REG,16);
    TEST_FIELD_RESET(ULPD_SETUP_VTCXO_REG,SETUP_VTCXO,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_CLOCK_CTRL_REG,16);
    TEST_FIELD_RESET(ULPD_CLOCK_CTRL_REG,SLICER_BYPASS,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SOFT_REQ_REG,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_IO_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_UWIRE_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_MMC2_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_MMC_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_UART3_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_UART2_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_UART1_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_USB_OTG_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_USB_PVCI_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_MCSI_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_CAMERA_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_REQ_REG,SOFT_DPLL_REQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_STATUS_REQ_REG,16);
    //ULPD_STATUS_REQ_REG,CAMERA of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,UART3 of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,UART2 of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,UART1 of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,MMC_REQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,MMC2_REQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,CLK_IO_REQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,USB_OTG_REQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,USB_PVCI_REQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,WAKEUP_NREQ of ULPD_STATUS_REQ_REG has unknown reset value;
    //ULPD_STATUS_REQ_REG,CHIP_IDLE of ULPD_STATUS_REQ_REG has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_APLL_CTRL_STATUS,16);
    //ULPD_APLL_CTRL_STATUS,LOCK_STATUS of ULPD_APLL_CTRL_STATUS has unknown reset value;
    TEST_FIELD_RESET(ULPD_APLL_CTRL_STATUS,PLL_CTRL_RES,16);
    TEST_FIELD_RESET(ULPD_APLL_CTRL_STATUS,PLL_CONTROL,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_POWER_CTRL_REG,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,DISABLE_RF_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,ENABLE_RF_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,VMODE_CONTROL,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,ISOLATION_CONTROL,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,MIN_MAX_REG,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,DVS_ENABLE,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,OSC_STOP_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,SOFT_LDO_SLEEP,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,LDO_CTRL_EN,16);
    //ULPD_POWER_CTRL_REG,LDO_STEADY of ULPD_POWER_CTRL_REG has unknown reset value;
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,POWERSEL_SLICER,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,DEEP_SLEEP_TRANSITION_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,VMODE_CTRL_DYNAMIC_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,DIS_HW_RF_BG_EN,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,LOW_PWR_REQ,16);
    TEST_FIELD_RESET(ULPD_POWER_CTRL_REG,LOW_PWR_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SLEEP_STATUS,16);
    //ULPD_SLEEP_STATUS,USB_PVCI_REQ of ULPD_SLEEP_STATUS has unknown reset value;
    //ULPD_SLEEP_STATUS,BIG_SLEEP of ULPD_SLEEP_STATUS has unknown reset value;
    //ULPD_SLEEP_STATUS,DEEP_SLEEP of ULPD_SLEEP_STATUS has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SETUP_RF_REG,16);
    TEST_FIELD_RESET(ULPD_SETUP_RF_REG,SETUP_RF,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SOFT_DISABLE_REQ_REG,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_CAMERA_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART3_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART2_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_UART1_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC2_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_MMC_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_PVCI_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_USB_OTG_REQ,16);
    TEST_FIELD_RESET(ULPD_SOFT_DISABLE_REQ_REG,DIS_CLK_IO_REQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_RESET_STATUS,16);
    TEST_FIELD_RESET(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_3,16);
    TEST_FIELD_RESET(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_2,16);
    TEST_FIELD_RESET(ULPD_RESET_STATUS,EXTERNAL_RESET_SOURCE_1,16);
    TEST_FIELD_RESET(ULPD_RESET_STATUS,POWER_ON_RESET,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_REVISION_NUMBER,16);
    //ULPD_REVISION_NUMBER,REVISION_NUMBER of ULPD_REVISION_NUMBER has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_CLK_IO_CTRL_REG,16);
    TEST_FIELD_RESET(ULPD_CLK_IO_CTRL_REG,CLK_IO_26M_DIV2,16);
    TEST_FIELD_RESET(ULPD_CLK_IO_CTRL_REG,CLK_IO_INV,16);
    TEST_FIELD_RESET(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_SEL,16);
    TEST_FIELD_RESET(ULPD_CLK_IO_CTRL_REG,CLK_IO_CLK_SEL,16);
    TEST_FIELD_RESET(ULPD_CLK_IO_CTRL_REG,CLK_IO_RATIO_REQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_ENA_MEMORY_RETENTION_REG,16);
    TEST_FIELD_RESET(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVDD,16);
    TEST_FIELD_RESET(ULPD_ENA_MEMORY_RETENTION_REG,EN_SPLZVSS,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_INC_FRAC_REG,16);
    TEST_FIELD_RESET(ULPD_INC_FRAC_REG,INC_FRAC,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_INC_SIXTEENTH_REG,16);
    TEST_FIELD_RESET(ULPD_INC_SIXTEENTH_REG,INC_SIXTEENTH,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SETUP_FRAME_REG,16);
    TEST_FIELD_RESET(ULPD_SETUP_FRAME_REG,SETUP_FRAME,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_GSM_TIMER_INIT_REG,16);
    TEST_FIELD_RESET(ULPD_GSM_TIMER_INIT_REG,TIMER_INIT,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_GSM_TIMER_IT_REG,16);
    TEST_FIELD_RESET(ULPD_GSM_TIMER_IT_REG,IT_GSM_TIMER,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_GSM_TIMER_VALUE_REG,16);
    TEST_FIELD_RESET(ULPD_GSM_TIMER_VALUE_REG,TIMER_VALUE,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_GSM_TIMER_CTRL_REG,16);
    TEST_FIELD_RESET(ULPD_GSM_TIMER_CTRL_REG,FREEZE,16);
    TEST_FIELD_RESET(ULPD_GSM_TIMER_CTRL_REG,LOAD,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_CLOCK_GSM_REG,16);
    TEST_FIELD_RESET(ULPD_CLOCK_GSM_REG,CLOCK_GSM_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_CLOCK_26M_CTRL,16);
    TEST_FIELD_RESET(ULPD_CLOCK_26M_CTRL,DIV2_26M_EN,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_ARM_GSM_COUNTER_LSB_REG,16);
    TEST_FIELD_RESET(ULPD_ARM_GSM_COUNTER_LSB_REG,TIMER_VALUE,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_ARM_GSM_COUNTER_MSB_REG,16);
    //ULPD_ARM_GSM_COUNTER_MSB_REG,DEEP_SLEEP_STATUS of ULPD_ARM_GSM_COUNTER_MSB_REG has unknown reset value;
    TEST_FIELD_RESET(ULPD_ARM_GSM_COUNTER_MSB_REG,TIMER_VALUE,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_DSP_GSM_COUNTER_LSB_REG,16);
    TEST_FIELD_RESET(ULPD_DSP_GSM_COUNTER_LSB_REG,TIMER_VALUE,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_DSP_GSM_COUNTER_MSB_REG,16);
    //ULPD_DSP_GSM_COUNTER_MSB_REG,DEEP_SLEEP_STATUS of ULPD_DSP_GSM_COUNTER_MSB_REG has unknown reset value;
    TEST_FIELD_RESET(ULPD_DSP_GSM_COUNTER_MSB_REG,TIMER_VALUE,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SIXTEENTH_START_REG,16);
    TEST_FIELD_RESET(ULPD_SIXTEENTH_START_REG,SIXTEENTH_START,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(ULPD_SIXTEENTH_STOP_REG,16);
    TEST_FIELD_RESET(ULPD_SIXTEENTH_STOP_REG,SIXTEENTH_STOP,16);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : ULPD_TestRegistersAccess
//
// DESCRIPTION : Test the access to ULPD registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void ULPD_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(ULPD_GAUGING_CTRL_REG,16);
    RW_PREPARE_WRITE(ULPD_GAUGING_CTRL_REG,OMAP_DPLL_DIV2,16);
    RW_PREPARE_WRITE(ULPD_GAUGING_CTRL_REG,GAUGING_TYPE,16);
    RW_PREPARE_WRITE(ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    RW_PREPARE_WRITE(ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    RW_WRITE(ULPD_GAUGING_CTRL_REG);
    RW_TEST_READ(ULPD_GAUGING_CTRL_REG,OMAP_DPLL_DIV2,16);
    RW_TEST_READ(ULPD_GAUGING_CTRL_REG,GAUGING_TYPE,16);
    RW_TEST_READ(ULPD_GAUGING_CTRL_REG,SELECT_HI_FREQ_CLOCK,16);
    RW_TEST_READ(ULPD_GAUGING_CTRL_REG,GAUGING_EN,16);
    RW_WRITE_PREVIOUS_VALUE(ULPD_GAUGING_CTRL_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(ULPD_SETUP_26M_REG,16);
    RW_PREPARE_WRITE(ULPD_SETUP_26M_REG,SETUP_26M,16);
    RW_WRITE(ULPD_SETUP_26M_REG);
    RW_TEST_READ(ULPD_SETUP_26M_REG,SETUP_26M,16);
    RW_WRITE_PREVIOUS_VALUE(ULPD_SETUP_26M_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(ULPD_SETUP_SLICER_REG,16);
    RW_PREPARE_WRITE(ULPD_SETUP_SLICER_REG,SETUP_SLICER,16);
    RW_WRITE(ULPD_SETUP_SLICER_REG);
    RW_TEST_READ(ULPD_SETUP_SLICER_REG,SETUP_SLICER,16);
    RW_WRITE_PREVIOUS_VALUE(ULPD_SETUP_SLICER_REG);