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📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
						
		break;
	    }//DMA_CONFIG8_8_5

	case DMA_CONFIG8_8_6:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_NO_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_SINGLE_INDEX;
		Chptr->DestAddressMode = DMA_ADD_SINGLE_INDEX;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 25;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 2;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
						
		break;
	    }//DMA_CONFIG8_8_6

	case DMA_CONFIG8_8_10:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_NO_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_SYNC_1;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 25;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
						
		break;
	    }//DMA_CONFIG8_8_10

	case DMA_CONFIG8_16_1:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 26;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 5;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 12;
						
		break;
	    }//DMA_CONFIG8_16_1

	case DMA_CONFIG8_16_2:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 26;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 5;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 12;
				
		break;
	    }//DMA_CONFIG8_16_2

	case DMA_CONFIG8_32_1:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_BURST_4;
		Chptr->DestBurst = DMA_BURST_8;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 28;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 12;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 5;
				
		break;
	    }//DMA_CONFIG8_32_1

	case DMA_CONFIG8_32_2:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 28;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 12;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 5;
				
		break;
	    }//DMA_CONFIG8_32_2

	case DMA_CONFIG16_8_1:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 26;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 1;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
		
		break;
	    }//DMA_CONFIG16_8_1

	case DMA_CONFIG16_8_2:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_8_BITS;
		
		Chptr->SrcPack = DMA_PACKING;
		Chptr->DestPack = DMA_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 26;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 1;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
				
		break;
	    }//DMA_CONFIG16_8_2

	case DMA_CONFIG16_16_1:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_16_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_NO_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 64;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
				
		break;
	    }//DMA_CONFIG16_16_1

	case DMA_CONFIG16_16_2:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_16_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_NO_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 64;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
				
		break;
	    }//DMA_CONFIG16_16_2

	case DMA_CONFIG16_16_3:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_16_BITS;
		
		Chptr->SrcPack = DMA_NO_PACKING;
		Chptr->DestPack = DMA_NO_PACKING;
		
		Chptr->SrcBurst = DMA_SINGLE_BURST;
		Chptr->DestBurst = DMA_SINGLE_BURST;
		
		//DMA_CCR
		//-----------------------
		Chptr->SyncNumb = DMA_NOT_SYNC;
		Chptr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
		Chptr->Priority = DMA_HIGH_PRIORITY;
		//  Chptr->Enable = ;
		Chptr->Autoinit = DMA_AUTOINIT_OFF;
		Chptr->Fifofush = DMA_NO_FLUSH;
		
		Chptr->SrcAddressMode = DMA_ADD_POSTINC;
		Chptr->DestAddressMode = DMA_ADD_POSTINC;
		
		//DMA_CEN 
		//----------------------
		Chptr->EltNumber = 64;
		
		//DMA_CFN 
		//----------------------
		Chptr->FrameNumber = 3;
		
		//DMA_CEI 
		//----------------------
		Chptr->EltIndex = 0;
		
		//DMA_CFI 
		//----------------------
		Chptr->FrameIndex = 0;
				
		break;
	    }//DMA_CONFIG16_16_3

	case DMA_CONFIG16_16_4:
	    {
		//DMA_CSDP
		//--------------------
		Chptr->TypeSize = DMA_TYPE_16_BITS;
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