aes.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : neptune_aes.c
//   Date of Module Modification:3/19/04
//   Date of Generation :3/19/04
//
//===============================================================================
#include "global_types.h"
#include "aes.h"
#include "errorcodes.h"
#include "testaccess.h"


//---------------------------------------------------------------------
// NAME        : AES_TestResetValue
//
// DESCRIPTION : Test the reset values of AES registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void AES_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(AES_AES_KEY4_L,32);
    TEST_FIELD_RESET(AES_AES_KEY4_L,KEY4,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY4_H,32);
    TEST_FIELD_RESET(AES_AES_KEY4_H,KEY4,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY3_L,32);
    TEST_FIELD_RESET(AES_AES_KEY3_L,KEY3,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY3_H,32);
    TEST_FIELD_RESET(AES_AES_KEY3_H,KEY3,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY2_L,32);
    TEST_FIELD_RESET(AES_AES_KEY2_L,KEY2,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY2_H,32);
    TEST_FIELD_RESET(AES_AES_KEY2_H,KEY2,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY1_L,32);
    TEST_FIELD_RESET(AES_AES_KEY1_L,KEY1,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_KEY1_H,32);
    TEST_FIELD_RESET(AES_AES_KEY1_H,KEY1,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_IV_1,32);
    TEST_FIELD_RESET(AES_AES_IV_1,IV,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_IV_2,32);
    TEST_FIELD_RESET(AES_AES_IV_2,IV,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_IV_3,32);
    TEST_FIELD_RESET(AES_AES_IV_3,IV,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_IV_4,32);
    TEST_FIELD_RESET(AES_AES_IV_4,IV,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_CTRL,32);
    TEST_FIELD_RESET(AES_AES_CTRL,RESERVED,32);
    TEST_FIELD_RESET(AES_AES_CTRL,CBC,32);
    TEST_FIELD_RESET(AES_AES_CTRL,KEY_SIZE,32);
    TEST_FIELD_RESET(AES_AES_CTRL,DIRECTION,32);
    TEST_FIELD_RESET(AES_AES_CTRL,INPUT_READY,32);
    TEST_FIELD_RESET(AES_AES_CTRL,OUTPUT_READY,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_DATA_1,32);
    TEST_FIELD_RESET(AES_AES_DATA_1,DATA,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_DATA_2,32);
    TEST_FIELD_RESET(AES_AES_DATA_2,DATA,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_DATA_3,32);
    TEST_FIELD_RESET(AES_AES_DATA_3,DATA,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_DATA_4,32);
    TEST_FIELD_RESET(AES_AES_DATA_4,DATA,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_REV,32);
    TEST_FIELD_RESET(AES_AES_REV,RESERVED,32);
    TEST_FIELD_RESET(AES_AES_REV,REV_NB,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_MASK,32);
    TEST_FIELD_RESET(AES_AES_MASK,RESERVED,32);
    TEST_FIELD_RESET(AES_AES_MASK,START,32);
    TEST_FIELD_RESET(AES_AES_MASK,DIRECT_BUS_EN,32);
    TEST_FIELD_RESET(AES_AES_MASK,DMA_REQ_OUT_EN,32);
    TEST_FIELD_RESET(AES_AES_MASK,DMA_REQ_IN_EN,32);
    TEST_FIELD_RESET(AES_AES_MASK,SOFTRESET,32);
    TEST_FIELD_RESET(AES_AES_MASK,AUTOIDLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(AES_AES_SYSSTATUS,32);
    TEST_FIELD_RESET(AES_AES_SYSSTATUS,RESERVED,32);
    TEST_FIELD_RESET(AES_AES_SYSSTATUS,RESETDONE,32);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : AES_TestRegistersAccess
//
// DESCRIPTION : Test the access to AES registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void AES_TestIVRegistersAccess(void) {
 BEGIN_ACCESS_MODULE();
 
    BEGIN_RW_TEST(AES_AES_IV_1,32);           // Could not reread IV is decrypt mode ?? (verilog)
    RW_PREPARE_WRITE(AES_AES_IV_1,IV,32);
    RW_WRITE(AES_AES_IV_1);
    RW_TEST_READ(AES_AES_IV_1,IV,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_IV_1);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_IV_2,32);
    RW_PREPARE_WRITE(AES_AES_IV_2,IV,32);
    RW_WRITE(AES_AES_IV_2);
    RW_TEST_READ(AES_AES_IV_2,IV,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_IV_2);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_IV_3,32);
    RW_PREPARE_WRITE(AES_AES_IV_3,IV,32);
    RW_WRITE(AES_AES_IV_3);
    RW_TEST_READ(AES_AES_IV_3,IV,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_IV_3);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_IV_4,32);
    RW_PREPARE_WRITE(AES_AES_IV_4,IV,32);
    RW_WRITE(AES_AES_IV_4);
    RW_TEST_READ(AES_AES_IV_4,IV,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_IV_4);
    END_RW_TEST();
    
  END_ACCESS_MODULE();
}

void AES_TestDATARegistersAccess(void) {
  BEGIN_ACCESS_MODULE();
    BEGIN_RW_TEST(AES_AES_DATA_1,32);
    RW_PREPARE_WRITE(AES_AES_DATA_1,DATA,32);
    RW_WRITE(AES_AES_DATA_1);
    RW_TEST_READ(AES_AES_DATA_1,DATA,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_DATA_1);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_DATA_2,32);
    RW_PREPARE_WRITE(AES_AES_DATA_2,DATA,32);
    RW_WRITE(AES_AES_DATA_2);
    RW_TEST_READ(AES_AES_DATA_2,DATA,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_DATA_2);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_DATA_3,32);
    RW_PREPARE_WRITE(AES_AES_DATA_3,DATA,32);
    RW_WRITE(AES_AES_DATA_3);
    RW_TEST_READ(AES_AES_DATA_3,DATA,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_DATA_3);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_DATA_4,32);
    RW_PREPARE_WRITE(AES_AES_DATA_4,DATA,32);
    RW_WRITE(AES_AES_DATA_4);
    RW_TEST_READ(AES_AES_DATA_4,DATA,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_DATA_4);
    END_RW_TEST();
  END_ACCESS_MODULE();
}
void AES_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

/*    BEGIN_RW_TEST(AES_AES_KEY4_L,32);
    RW_PREPARE_WRITE(AES_AES_KEY4_L,KEY4,32);
    RW_WRITE(AES_AES_KEY4_L);
    RW_TEST_READ(AES_AES_KEY4_L,KEY4,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY4_L);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY4_H,32);
    RW_PREPARE_WRITE(AES_AES_KEY4_H,KEY4,32);
    RW_WRITE(AES_AES_KEY4_H);
    RW_TEST_READ(AES_AES_KEY4_H,KEY4,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY4_H);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY3_L,32);
    RW_PREPARE_WRITE(AES_AES_KEY3_L,KEY3,32);
    RW_WRITE(AES_AES_KEY3_L);
    RW_TEST_READ(AES_AES_KEY3_L,KEY3,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY3_L);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY3_H,32);
    RW_PREPARE_WRITE(AES_AES_KEY3_H,KEY3,32);
    RW_WRITE(AES_AES_KEY3_H);
    RW_TEST_READ(AES_AES_KEY3_H,KEY3,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY3_H);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY2_L,32);
    RW_PREPARE_WRITE(AES_AES_KEY2_L,KEY2,32);
    RW_WRITE(AES_AES_KEY2_L);
    RW_TEST_READ(AES_AES_KEY2_L,KEY2,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY2_L);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY2_H,32);
    RW_PREPARE_WRITE(AES_AES_KEY2_H,KEY2,32);
    RW_WRITE(AES_AES_KEY2_H);
    RW_TEST_READ(AES_AES_KEY2_H,KEY2,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY2_H);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY1_L,32);
    RW_PREPARE_WRITE(AES_AES_KEY1_L,KEY1,32);
    RW_WRITE(AES_AES_KEY1_L);
    RW_TEST_READ(AES_AES_KEY1_L,KEY1,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY1_L);
    END_RW_TEST();

    BEGIN_RW_TEST(AES_AES_KEY1_H,32);
    RW_PREPARE_WRITE(AES_AES_KEY1_H,KEY1,32);
    RW_WRITE(AES_AES_KEY1_H);
    RW_TEST_READ(AES_AES_KEY1_H,KEY1,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_KEY1_H);
    END_RW_TEST();
*/

/*    BEGIN_RW_TEST(AES_AES_CTRL,32);
    RW_PREPARE_WRITE(AES_AES_CTRL,RESERVED,32);
    RW_PREPARE_WRITE(AES_AES_CTRL,CBC,32);
    RW_PREPARE_WRITE(AES_AES_CTRL,KEY_SIZE,32);
    RW_PREPARE_WRITE(AES_AES_CTRL,DIRECTION,32);
    AES_AES_CTRL,INPUT_READY is Read Only
    AES_AES_CTRL,OUTPUT_READY is Read Only
    RW_WRITE(AES_AES_CTRL);
    RW_TEST_READ(AES_AES_CTRL,RESERVED,32);
    RW_TEST_READ(AES_AES_CTRL,CBC,32);
    RW_TEST_READ(AES_AES_CTRL,KEY_SIZE,32);
    RW_TEST_READ(AES_AES_CTRL,DIRECTION,32);
    AES_AES_CTRL,INPUT_READY is Read Only
    AES_AES_CTRL,OUTPUT_READY is Read Only
    RW_WRITE_PREVIOUS_VALUE(AES_AES_CTRL);
    END_RW_TEST();
*/


    BEGIN_RW_TEST(AES_AES_MASK,32);
//    RW_PREPARE_WRITE(AES_AES_MASK,RESERVED,32);
//    RW_PREPARE_WRITE(AES_AES_MASK,START,32);
    RW_PREPARE_WRITE(AES_AES_MASK,DIRECT_BUS_EN,32);
    RW_PREPARE_WRITE(AES_AES_MASK,DMA_REQ_OUT_EN,32);
    RW_PREPARE_WRITE(AES_AES_MASK,DMA_REQ_IN_EN,32);
//    RW_PREPARE_WRITE(AES_AES_MASK,SOFTRESET,32);
    RW_PREPARE_WRITE(AES_AES_MASK,AUTOIDLE,32);
    RW_WRITE(AES_AES_MASK);
//    RW_TEST_READ(AES_AES_MASK,RESERVED,32);
//    RW_TEST_READ(AES_AES_MASK,START,32);
    RW_TEST_READ(AES_AES_MASK,DIRECT_BUS_EN,32);
    RW_TEST_READ(AES_AES_MASK,DMA_REQ_OUT_EN,32);
    RW_TEST_READ(AES_AES_MASK,DMA_REQ_IN_EN,32);
//    RW_TEST_READ(AES_AES_MASK,SOFTRESET,32);
    RW_TEST_READ(AES_AES_MASK,AUTOIDLE,32);
    RW_WRITE_PREVIOUS_VALUE(AES_AES_MASK);
    END_RW_TEST();

  END_ACCESS_MODULE();

}

void AES_SetControlDirection() {
    AES_AES_CTRL |=  (UWORD32)(1<<AES_AES_CTRL_DIRECTION_POS);
}

void AES_SetControlCBC() {
    AES_AES_CTRL |=  (UWORD32)(1<<AES_AES_CTRL_CBC_POS);
}

void AES_ClearControlDirection() {
    AES_AES_CTRL &=  (UWORD32)(!(1<<AES_AES_CTRL_DIRECTION_POS));
}

BOOL AES_InputReady() {
    return (BOOL)(AES_AES_CTRL & (UWORD32)(1<<AES_AES_CTRL_INPUT_READY_POS));
}

BOOL AES_OutputReady() {
    return (BOOL)(AES_AES_CTRL & (UWORD32)(1<<AES_AES_CTRL_OUTPUT_READY_POS));
}