guarttest.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*  
  //Used to clear FIFO 
  UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
                  UARTMOD_CLEAR_RX_FIFO,
                  UARTMOD_CLEAR_TX_FIFO,
                  UARTMOD_DMA_MODE_0,
                  UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
                  UARTMOD_RX_8_CHARS_FIFO_TRIGGER);
  
  //--- Program FIFO and DMA mode  ---
  // FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
  // DMA mode 0 for used mask dma_reg,  trig. TX FIFO , trig.RX FIFO
  UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
                  UARTMOD_NOCHANGE_RX_FIFO,
                  UARTMOD_NOCHANGE_TX_FIFO,
                  UARTMOD_DMA_MODE_0, 
                  UARTMOD_TX_16_SPACES_FIFO_TRIGGER,
                  UARTMOD_RX_16_CHARS_FIFO_TRIGGER);  
  
*/  
  
    //_____________________________________________________

  // --- Force signal emulating modem control exchange --- 

  // Force loopback config  
  UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
                  UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
                  UARTMOD_LOOPBACK, 
                  UARTMOD_DISABLE_XON_ANY_FCT,
                  UARTMOD_DISABLE_TCR_TLR_ACCESS,
                  UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,  // Force loopback config
                  UartType);    
  
  iir= UMOD_ReadIir(UartType);
  
  //mode select :start up after config registers DLL,DLH,LCR ..  
  UMOD_InitMdr1(UARTMOD_UART_SELECT,UartType);
  
  // --- init interrupts  ---
  //Set no Interrupt config and set disable sleep mode for config divisor latches 
  UMOD_InitIer(UARTMOD_MASK_RHR_IT,
                  UARTMOD_MASK_THR_IT,
                  UARTMOD_MASK_LINE_STS_IT,
                  UARTMOD_MASK_MODEM_STS_IT,
                  UARTMOD_MASK_SLEEP_MODE,
                  UARTMOD_MASK_XOFF_IT,
                  UARTMOD_MASK_RTS_IT,
                  UARTMOD_MASK_CTS_IT,
                  UartType);
  
  
  // read line status register
  lsr = UMOD_ReadLsr(UartType);    
  
  
  return(status_result);
}



//================================================================================
// NAME       : UTST_ModemWithDma
// DESCRIPTION: performs uart test in DMA mode (uart is in internal loopback)
//              Transfers are done from and to EMIF  slow (CS0)
//  Disable DMA Channel 0 & 1 
//  Configure UART in Loop Back TX --> RX                                 
//  Write overflow data Into destination area 
//  Fill DATA to be transfered
//  Enable channel 0 & 1
//  Wait for IT DMA of Sending  
//  Disable Transmitter Channel #0        
//  Wait for IT DMA of Reception                      
//  Check the data read match the written data        
//   and that the overflow area is not overwritten                  
//                                      
// PARAMETERS  : 
//    emif_src_address,
//    emif_dst_address
//    nb_byte_to_transmit
//    end_dma_channel_0 
//    end_dma_channel_1
// RESTRICTION : source and destination address should correspond to EMIF slow Interface
//            nb_byte_to_transmit should be a multiple of 4
// RETURN VALUE: RES_OK on success otherwise RES_BAD                   
//================================================================================


UWORD16 UTST_ModemWithDma(UWORD32 emif_src_address,
                                UWORD32 emif_dst_address,
                                UWORD8  nb_byte_to_transmit,
                                volatile BOOL * const end_dma_channel_0, 
                                volatile BOOL * const end_dma_channel_1,
                                CHANNEL_DESCRIPTOR* ChannelPtr,
                                UARTMOD_UartType_t UartType)
  
{
  UWORD8 * ptr_tx_buffer;
  UWORD8 * ptr_rx_buffer; // one byte more for checking overflow
  UWORD8 i;
  BOOL ok;
  UWORD8 statusmodem,iir;  
  UWORD8 TX_Latch, RX_Latch;

  ptr_tx_buffer = (UWORD8 *) emif_src_address ;
  ptr_rx_buffer = (UWORD8 *) emif_dst_address ;
    
  UTST_InitUartModem (UartType); 
  statusmodem= UMOD_ReadLsr(UartType);
  iir= UMOD_ReadIir(UartType);
  
  //----------------------------------------------------
  // 1) DISABLE CHANNELS 0 & 1
  //----------------------------------------------------
  DMA_DisableChannel(DMA_CHANNEL_0); /* disable transmit dma channel */
  DMA_DisableChannel(DMA_CHANNEL_1); /* disable rx dma channel */
  
  
  //----------------------------------------------------
  // 2) CONFIGURE UART
  //----------------------------------------------------
  //DMA MODE FIFO CONTROL REGISTER (FCR) not used , 
  //Supplement Control Register set DMA MODE
  //DMA Mode 2 ARM_nDMA_REQ[0] in TX UART MODEM 

  UMOD_InitScr(UARTMOD_FCR_SET_DMA_MODE  , 
                  UARTMOD_nDMA_REQ_0_in_TX_1_in_RX, 
                  UARTMOD_THR_IT_NORMAL_MODE, 
                  UARTMOD_NO_WAKEUP, 
                  UARTMOD_MASK_DSR_IT,
                  UartType);
  
  //trigger Level register (4)
  UMOD_InitTlr(UARTMOD_TX_FIFO_TRIG_DMA_4_TO_FILLUP,
                  UARTMOD_RX_FIFO_TRIG_DMA_4_TO_GET,
                  UartType);
  
  
  iir= UMOD_ReadIir(UartType);
  
  //----------------------------------------------------------
  // init. to check transfer overflow 
  //----------------------------------------------------------
  * (ptr_rx_buffer + nb_byte_to_transmit)=0x55;
  
  //--------------------------------------------------------------
  // Fill DATA into memory
  // to send to UART MODEM Rhea peripheral                    -
  //--------------------------------------------------------------
  for (i=0; i <nb_byte_to_transmit; i++)
    *(ptr_tx_buffer+i) = i+INITIAL_VALUE;
  
  
  
  //===============================================================
  // Configure DMA channel 0 for rx to modem

  //-------------------------------------------- 
  //DMA_CSDP
  ChannelPtr->TypeSize  = DMA_TYPE_8_BITS;  
  ChannelPtr->SrcPack   = DMA_NO_PACKING;
  ChannelPtr->DestPack  = DMA_NO_PACKING;
  ChannelPtr->SrcBurst  = DMA_SINGLE_BURST;
  ChannelPtr->DestBurst = DMA_SINGLE_BURST;
  //-------------------------------------------- 
  //DMA_CCR
  ChannelPtr->SyncNumb  = DMA_NOT_SYNC;
  ChannelPtr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
  ChannelPtr->Priority  = DMA_HIGH_PRIORITY;
  ChannelPtr->Autoinit  = DMA_AUTOINIT_OFF;
  ChannelPtr->Fifofush  = DMA_FORCE_FLUSH;
  ChannelPtr->SrcAddressMode  = DMA_ADD_CONSTANT;
  ChannelPtr->DestAddressMode = DMA_ADD_POSTINC;
  //-------------------------------------------- 
  //DMA_CEN 
  ChannelPtr->EltNumber   = nb_byte_to_transmit;
  //--------------------------------------------
  //DMA_CFN
  ChannelPtr->FrameNumber = 1;
  //--------------------------------------------
  //DMA_CEI 
  ChannelPtr->EltIndex    = 0;
  //--------------------------------------------
  //DMA_CFI 
  ChannelPtr->FrameIndex  = 0;
  //--------------------------------------------
  //DMA_CSSA L and U
  ChannelPtr->SrcAdd=UARTMOD_RHR_REG(UartType);
  //--------------------------------------------
  //DMA_CDSA L and U
  ChannelPtr->DestAdd=FREE_MEM;
  //--------------------------------------------
  //DMA_CEN 
  ChannelPtr->ChannelNumb = 0;
    
  SDMA_SetupChannelStruct(ChannelPtr);  
  
  //===============================================================
  // Configure DMA channel 1 for tx from modem
  
  //-------------------------------------------- 
  //DMA_CSDP
  ChannelPtr->TypeSize  = DMA_TYPE_8_BITS;  
  ChannelPtr->SrcPack   = DMA_NO_PACKING;
  ChannelPtr->DestPack  = DMA_NO_PACKING;
  ChannelPtr->SrcBurst  = DMA_SINGLE_BURST;
  ChannelPtr->DestBurst = DMA_SINGLE_BURST;
  //-------------------------------------------- 
  //DMA_CCR
  ChannelPtr->SyncNumb  = DMA_NOT_SYNC;
  ChannelPtr->EventSync = DMA_FRAME_SYNCHRONIZED;//fs
  ChannelPtr->Priority  = DMA_HIGH_PRIORITY;
  ChannelPtr->Autoinit  = DMA_AUTOINIT_OFF;
  ChannelPtr->Fifofush  = DMA_FORCE_FLUSH;
  ChannelPtr->SrcAddressMode  = DMA_ADD_CONSTANT;
  ChannelPtr->DestAddressMode = DMA_ADD_POSTINC;
  //-------------------------------------------- 
  //DMA_CEN 
  ChannelPtr->EltNumber   = nb_byte_to_transmit;
  //--------------------------------------------
  //DMA_CFN
  ChannelPtr->FrameNumber = 1;
  //--------------------------------------------
  //DMA_CEI 
  ChannelPtr->EltIndex    = 0;
  //--------------------------------------------
  //DMA_CFI 
  ChannelPtr->FrameIndex  = 0;
  //--------------------------------------------
  //DMA_CSSA L and U
  ChannelPtr->SrcAdd=FREE_MEM;
  //--------------------------------------------
  //DMA_CDSA L and U
  ChannelPtr->DestAdd=UARTMOD_THR_REG(UartType);
  //--------------------------------------------
  //DMA_CEN 
  ChannelPtr->ChannelNumb = 1;

  SDMA_SetupChannelStruct(ChannelPtr);  
  
  //----------------------------------------------------
  //  ENABLE CHANNELS 0 & 1
  //----------------------------------------------------
  *end_dma_channel_0=False;
  *end_dma_channel_1=False;
  
  DMA_EnableChannel(DMA_CHANNEL_0); /* enable transmit dma channel */
  DMA_EnableChannel(DMA_CHANNEL_1); /* enable receive  dma channel */
  
  // write again in SCR register for generating a new Dma_nrequest
  UMOD_InitScr(UARTMOD_SCR_SET_DMA_MODE, 
                  UARTMOD_nDMA_REQ_0_in_TX_1_in_RX, 
                  UARTMOD_THR_IT_NORMAL_MODE, 
                  UARTMOD_NO_WAKEUP, 
                  UARTMOD_MASK_DSR_IT,
                  UartType);
                  
  // We need the 32 kHz in big/deep sleep mode
  ULPD_SetParameters(MODEM_32K_12M_PASSING,COM_CLOCK_INACTIV_0,SDW_CLOCK_INACTIV_0);
  
  CLKA_ConfigIdleModule(SET_IN_IDLE,   //TimState
                   SET_NOT_IDLE,  //DpllState
                   SET_NOT_IDLE,  //IntMemState (dma, mem ...)
                   SET_IN_IDLE,   //LcdState
                   SET_NOT_IDLE,  //PerState
                   SET_NOT_IDLE,  //XorpState
                   SET_IN_IDLE);  //WdtState

  // Wait for an interrupt (if interrput isn't come yet)
  if (*end_dma_channel_0 == False)
    CLKA_SetIdle(IDLE_WAITFOR_INT_WKUP);

  
  //---------------------------------------------------
  // WAIT FOR of end of Transmission DMA IT
  //---------------------------------------------------
  while (*end_dma_channel_0 ==False);
  
  
  //----------------------------------------------------------
  //  Disable  DMA channel 0                              
  //----------------------------------------------------------   
  DMA_DisableChannel(DMA_CHANNEL_0); /* disable transmit dma channel */
  
  //----------------------------------------------------------
  // Wait for IT DMA of Reception                        -
  //----------------------------------------------------------  
  while (*end_dma_channel_1==False) ;
  
  
  //--------------------------------------------------------------------
  // Check the data read match the written data        
  //     and that the overflow area is not overwritten                 -
  //-------------------------------------------------------------------- 
  ok=True;
  for (i=0; i<nb_byte_to_transmit; i++)
  {
    TX_Latch=*(ptr_tx_buffer+i);
    RX_Latch=*(ptr_rx_buffer+i);
    if ( TX_Latch != RX_Latch )
    {
      RES_Set(UARTTEST_BAD_READ_VALUE);
      //Expected value
      RES_Set(DATA_STORE);
      RES_Set(TX_Latch);
      // Value effectively read
      RES_Set(DATA_STORE);
      RES_Set(RX_Latch);
      
      ok=False;
    }
  }

  // check dma overflow
  if (*(ptr_rx_buffer+nb_byte_to_transmit)!=0x55)
  {
    RES_Set(UARTTEST_DMA_OVERFLOW);
    ok=False;
  }
  
  
  if (ok) 
    return(RES_OK);
  else
    return(RES_BAD);
  
}



//================================================================================
// NAME       : UTST_SetDivLatch

// DESCRIPTION: 
// This function initialises the latch that will be used to generate the baud
// clk in the baud rate generator.

// PARAMETERS  : 
//    DLL : 8 LSB divisor value
//    DLH : 8 MSB divisor value

// RETURN VALUE: true on success, false in any other case
//================================================================================
BOOL UTST_SetDivLatch(UWORD8 DLLInit, UWORD8 DLHInit,UARTMOD_UartType_t UartType)
{
 
  UMOD_InitDivLatch(DLLInit,DLHInit,UartType);
  
  if (UMOD_ReadDll(UartType) != DLLInit ||
      UMOD_ReadDlh(UartType) != DLHInit) 
  {
    RES_Set(UARTTEST_DLL_DLH_REG_INIT_ERROR);

    //Expected value to be read
    RES_Set(DATA_STORE);
    RES_Set(DLLInit | (DLHInit<<8));

    //Value read
    RES_Set(DATA_STORE);
    RES_Set(UMOD_ReadDll(UartType) | (UMOD_ReadDlh(UartType)<<8));
    
    return False;
  }
  
  return True;
}