📄 guarttest.c
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//=====================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
// Property of Texas Instruments -- For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited
// This product is protected under copyright law and trade secret law as
// an unpublished work.Created 2000,(C) Copyright 2000 Texas Instruments.
// All rights reserved.
// Filename : uarttest.c
// Description : file for the test UART connected to ARM9
// Project : Helen (Adapted from Perseus)
// Author : Francis Huguenin
// Adapted by Jean-Philippe Ulpiano
//=====================================================================
#include "guarttest.h"
#define INITIAL_VALUE 0x41
#define FREE_MEM 0xBAD
//================================================================================
// NAME : UTST_ModemBase
// DESCRIPTION:
// Test uart modem in loopback mode wich can be internal or external
// (via test bench)
// Data are sent by writng in Tx register
// Data are read by reading in Rx register
// PARAMETERS :
// nb_byte_to_transmit : number of byte transmitted and received in the test
// external_loopback : True of loopcak is extern (via testbench)
// modem_irq_count : counter of modem irq (should be used in interrupt routine)
// RETURN VALUE: RES_OK on success otherwise RES_BAD
//================================================================================
UWORD16 UTST_ModemBase(UWORD8 nb_byte_to_transmit,
BOOL external_loopback ,
UWORD8 * const modem_irq_count,
UARTMOD_UartType_t UartType)
{
UWORD8 val;
UWORD32 i;
UWORD32 nb;
UWORD8 status;
UWORD8 rxdata1;
UWORD8 mdr1, mdr3, ier1, ier2, iir1, iir2;
UWORD8 StatusModemSender, StatusModemReceiver;
UWORD32 SoftWDog;
BOOL ok = True;
//================================
// ----- INIT UART MODEM-----
//================================
//____________________________________________________________________
//--- Sequence to change baud rate ---
//Set register LCR=0xBF for access to EFR register
UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
UARTMOD_2_NB_STOP_BITS,
UARTMOD_PARITY_BIT,
UARTMOD_SPACE_PARITY_TYPE, //To check F reygagne
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_GRANT_DIVISOR_LATCH_ACCESS,
UartType);
//IER[7:4] can only modified and enabled if EFR[4] is set
UMOD_InitEfr(UARTMOD_RX_NO_FLOW,
UARTMOD_TX_NO_FLOW,
UARTMOD_ENABLE_WRITE_IER,
UARTMOD_DISABLE_SPECIAL_CHAR_DETECT,
UARTMOD_DISABLE_AUTO_RTS,
UARTMOD_DISABLE_AUTO_CTS,
UartType);
//set no Interrupt config & disable sleep mode for config divisor latches
ier1=UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
ok&=UTST_SetDivLatch(1,0,UartType);
//Disable sleep mode & Mask all modem IT
ier1=UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
//--- End sequence to change baud rate ---
//____________________________________________________________________
//____________________________________________________________________
//=====================================================
// --- Config trame ---
// 8 bits RX and Tx, 1 stop bit,
// parity trasmit Tx and check Rx, Even= 1, force 0 parity,
//Break control bit =0 , normal mode =0 */
UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
UARTMOD_1_NB_STOP_BITS,
UARTMOD_PARITY_BIT,
UARTMOD_EVEN_PARITY_TYPE,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_NO_DIVISOR_LATCH_ACCESS,
UartType);
// used for clear FIFO
UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
UARTMOD_CLEAR_RX_FIFO,
UARTMOD_CLEAR_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
UartType);
//=====================================================
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0,
// clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
// DMA mode 0 =1 single character transfers,
// trig. TX FIFO don't care , trig.RX FIFO don't care
UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
UARTMOD_NOCHANGE_RX_FIFO,
UARTMOD_NOCHANGE_TX_FIFO,
UARTMOD_DMA_MODE_1,
UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
UartType);
//=====================================================
// --- Force signal emulating modem control exchange ---
// Force DCD and RTS low
if(external_loopback)
// external loopback
UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
UARTMOD_NO_LOOPBACK,
UARTMOD_DISABLE_XON_ANY_FCT,
UARTMOD_ENABLE_TCR_TLR_ACCESS, //new field value to confirm
UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
UartType);
else
// internal loopback
UMOD_InitMcr(UARTMOD_FAX_MODE_ENABLE,
UARTMOD_OUTPUT_REQUEST_TO_SEND_ENABLE,
UARTMOD_LOOPBACK,
UARTMOD_DISABLE_XON_ANY_FCT,
UARTMOD_ENABLE_TCR_TLR_ACCESS, //new field value to confirm
UARTMOD_DIV_CLOCK_INPUT_NO_ACTION,
UartType);
iir1=UMOD_ReadIir(UartType);
*modem_irq_count =0;
//mode select :start up after config registers DLL,DLH,LCR ..
mdr1= UMOD_InitMdr1(UARTMOD_UART_SELECT,UartType);
//=====================================================
// --- Enable interrupts used
//Set Interrupt config
ier1 = UMOD_InitIer(UARTMOD_RHR_IT_ENABLE,
UARTMOD_THR_IT_ENABLE,
UARTMOD_LINE_STS_IT_ENABLE,
UARTMOD_MODEM_STS_IT_ENABLE,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_RTS_IT_ENABLE,
UARTMOD_CTS_IT_ENABLE,
UartType);
// Wait for THR empty interrupt
do
iir1= UMOD_ReadIir(UartType);
while ( *modem_irq_count == 0);
//--------------------------------------
// MODEM SEND VALUE
//--------------------------------------
for (i=0; i<nb_byte_to_transmit; i++)
UMOD_Send(i+ INITIAL_VALUE,UartType);
//----------------------------------------------
// CHECK STATUS OF MODEM SENDER -
//----------------------------------------------
StatusModemSender = UMOD_ReadLsr(UartType);
// Wait for transmit data to be ended : hold and shift register are empty
while ( UMOD_IsTransmitAndHoldRegNotEmpty(UartType) );
//-------------------------------------------
// CHECK STATUS OF MODEM RECEIVER -
//-------------------------------------------
StatusModemReceiver = UMOD_ReadLsr(UartType);
//--------------------------------------------------
// UART MODEM CATCH BACK THE CHARACTERS AND CHECK -
//--------------------------------------------------
i=0;
ok= True;
while (i < nb_byte_to_transmit)
// before reading verify that FIFO receive is not empty
if (UMOD_RxFifoIsNotEmpty(UartType))
{
val = UMOD_Read(UartType);
if (val != (i+ INITIAL_VALUE))
{
RES_Set(UARTTEST_BAD_READ_VALUE);
// Expected value:
RES_Set(DATA_STORE);
RES_Set(i+INITIAL_VALUE);
// Bad value read:
RES_Set(DATA_STORE);
RES_Set(val);
ok = False;
}
i++;
}
if (ok)
return(RES_OK);
else
return(RES_BAD);
}
//================================================================================
// UTST_InitUartModem
UWORD16 UTST_InitUartModem (UARTMOD_UartType_t UartType)
{
UWORD8 lsr,iir;
UWORD16 status_result = RES_OK;
UWORD8 DLLInit, DLHInit;
//==================================
// ----- INIT UART MODEM-----
//==================================
//_____________________________________________________
//--- Sequence to change baud rate ---
// set regiter LCR=0xBF for accsess to EFR register
UMOD_InitLcr(UARTMOD_8BITS_CHAR_LENGTH,
UARTMOD_2_NB_STOP_BITS,
UARTMOD_PARITY_BIT,
UARTMOD_SPACE_PARITY_TYPE,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_GRANT_DIVISOR_LATCH_ACCESS,
UartType);
// IER[7:4] can only modified and enabled if EFR[4] is set
UMOD_InitEfr(UARTMOD_RX_NO_FLOW,
UARTMOD_TX_NO_FLOW,
UARTMOD_ENABLE_WRITE_IER,
UARTMOD_DISABLE_SPECIAL_CHAR_DETECT,
UARTMOD_DISABLE_AUTO_RTS,
UARTMOD_DISABLE_AUTO_CTS,
UartType);
//Set no Interrupt config and set disable sleep mode for config divisor latches
UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
// write in fcr should be done before setting DLH and DLL register
//Used for clear FIFO
UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
UARTMOD_CLEAR_RX_FIFO,
UARTMOD_CLEAR_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_8_SPACES_FIFO_TRIGGER,
UARTMOD_RX_8_CHARS_FIFO_TRIGGER,
UartType);
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
// DMA mode 0 for used mask dma_reg, trig. TX FIFO , trig.RX FIFO
UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
UARTMOD_NOCHANGE_RX_FIFO,
UARTMOD_NOCHANGE_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_16_SPACES_FIFO_TRIGGER,
UARTMOD_RX_16_CHARS_FIFO_TRIGGER,
UartType);
//Set DLL to 0x01 and DLH to 0x00
status_result=UTST_SetDivLatch(0x01,0x00,UartType)==True ? RES_OK : RES_BAD;
//--- End sequence to change baud rate ---
//_____________________________________________________
//_____________________________________________________
// --- Config trame ---
// 8 bits RX and Tx, 1 stop bit, parity trasmit Tx and check Rx,
// Even= 1, force 0 parity,
// Break control bit =0 , normal mode =0
UMOD_InitLcr (UARTMOD_8BITS_CHAR_LENGTH,
UARTMOD_1_NB_STOP_BITS,
UARTMOD_PARITY_BIT,
UARTMOD_EVEN_PARITY_TYPE,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_NO_DIVISOR_LATCH_ACCESS,
UartType);
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