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📄 frame_counter.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
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//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION          
//
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work. 
//   Created 2000, (C) Copyright 2000 Texas Instruments.  All rights reserved.
//
//   Filename             : neptune_frame_counter.c
//   Date of Module Modification:4/22/04
//   Date of Generation :5/4/04
//
//===============================================================================
#include "global_types.h"
#include "frame_counter.h"
#include "errorcodes.h"
#include "testaccess.h"

//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_TestResetValue
//
// DESCRIPTION : Test the reset values of FRAME_COUNTER registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESERVED,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,EDGE_SELECTION,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,START,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESET,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG,PRELOAD_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCBSP1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCBSP1_REG,COUNTER_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESERVED,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,EDGE_SELECTION,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,START,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESET,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG,PRELOAD_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCSI1_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCSI1_REG,COUNTER_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESERVED,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,EDGE_SELECTION,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,START,32);
    TEST_FIELD_RESET(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESET,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG,PRELOAD_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCSI2_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_COUNTER_VALUE_SYNC_MCSI2_REG,COUNTER_VALUE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_REVISION_NUMBER_REG,32);
    //FRAME_COUNTER_REVISION_NUMBER_REG,REVISION_NUMBER of FRAME_COUNTER_REVISION_NUMBER_REG has unknown reset value;
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_OCP_CONTROL_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_CONTROL_REG,SOFTWARE_RESET,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_CONTROL_REG,OCP_IDLE,32);
    END_RESET_TEST();

    BEGIN_RESET_TEST(FRAME_COUNTER_OCP_RESET_STATUS_REG,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_RESET_STATUS_REG,SOFTWARE_RESET_3_STATUS,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_RESET_STATUS_REG,SOFTWARE_RESET_2_STATUS,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_RESET_STATUS_REG,SOFTWARE_RESET_1_STATUS,32);
    TEST_FIELD_RESET(FRAME_COUNTER_OCP_RESET_STATUS_REG,SOFTWARE_RESET_OCP,32);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_TestRegistersAccess
//
// DESCRIPTION : Test the access to FRAME_COUNTER registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,32);
    //FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESERVED is Read Only
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,EDGE_SELECTION,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,START,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESET,32);
    RW_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG);
    //FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESERVED is Read Only
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,EDGE_SELECTION,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,START,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG,RESET,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG,PRELOAD_VALUE,32);
    RW_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG);
    RW_TEST_READ(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG,PRELOAD_VALUE,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_PRELOAD_SYNC_MCBSP1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,32);
    //FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESERVED is Read Only
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,EDGE_SELECTION,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,START,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESET,32);
    RW_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG);
    //FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESERVED is Read Only
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,EDGE_SELECTION,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,START,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG,RESET,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG,PRELOAD_VALUE,32);
    RW_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG);
    RW_TEST_READ(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG,PRELOAD_VALUE,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_PRELOAD_SYNC_MCSI1_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,32);
    //FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESERVED is Read Only
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,EDGE_SELECTION,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,START,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESET,32);
    RW_WRITE(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG);
    //FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESERVED is Read Only
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,EDGE_SELECTION,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,START,32);
    RW_TEST_READ(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG,RESET,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG,PRELOAD_VALUE,32);
    RW_WRITE(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG);
    RW_TEST_READ(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG,PRELOAD_VALUE,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_PRELOAD_SYNC_MCSI2_REG);
    END_RW_TEST();

    BEGIN_RW_TEST(FRAME_COUNTER_OCP_CONTROL_REG,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_OCP_CONTROL_REG,SOFTWARE_RESET,32);
    RW_PREPARE_WRITE(FRAME_COUNTER_OCP_CONTROL_REG,OCP_IDLE,32);
    RW_WRITE(FRAME_COUNTER_OCP_CONTROL_REG);
    RW_TEST_READ(FRAME_COUNTER_OCP_CONTROL_REG,SOFTWARE_RESET,32);
    RW_TEST_READ(FRAME_COUNTER_OCP_CONTROL_REG,OCP_IDLE,32);
    RW_WRITE_PREVIOUS_VALUE(FRAME_COUNTER_OCP_CONTROL_REG);
    END_RW_TEST();

  END_ACCESS_MODULE();

}

//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_StartCounter
//
// DESCRIPTION : Start Counter
//
// PARAMETERS  : 	FC_MCBSP1	  	or       
//             		FC_MCSI1		or       
//		        FC_MCSI2		
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_StartCounter(FRAME_COUNTER_Type Fctype)
{
 switch (Fctype)
 {
  case FC_MCBSP1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_START_NUMB,1);	         
     break;	
    }

    case FC_MCSI1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_START_NUMB,1);	         
     break;	
    }

    case FC_MCSI2: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_START_NUMB,1);	         
     break;	
    }
  }
}

//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_StopCounter
//
// DESCRIPTION : Stop Counter
//
// PARAMETERS  : 	FC_MCBSP1	  	or       
//             		FC_MCSI1		or       
//		        FC_MCSI2		
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_StopCounter(FRAME_COUNTER_Type Fctype)
{
 switch (Fctype)
 {
  case FC_MCBSP1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_START_NUMB,0);	         
     break;	
    }

    case FC_MCSI1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_START_NUMB,0);	         
     break;	
    }

    case FC_MCSI2: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_START_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_START_NUMB,0);	         
     break;	
    }
  }
}



//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_ResetCounter
//
// DESCRIPTION : Reset Counter
//
// PARAMETERS  : 	FC_MCBSP1	  	or       
//             		FC_MCSI1		or       
//		        FC_MCSI2		
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_ResetCounter(FRAME_COUNTER_Type Fctype)
{
 switch (Fctype)
 {
  case FC_MCBSP1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_RESET_POS, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_RESET_NUMB,1);	         
     break;	
    }

    case FC_MCSI1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_RESET_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_RESET_NUMB,1);	         
     break;	
    }

    case FC_MCSI2: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_RESET_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_RESET_NUMB,1);	         
     break;	
    }
  }
}        
        
//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_RisingEdge
//
// DESCRIPTION : Counter works on Rising Edge 
//
// PARAMETERS  : 	FC_MCBSP1	  	or       
//             		FC_MCSI1		or       
//		        FC_MCSI2		
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_RisingEdge(FRAME_COUNTER_Type Fctype)
{
 switch (Fctype)
 {
  case FC_MCBSP1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_EDGE_SELECTION_NUMB,0);	         
     break;	
    }

    case FC_MCSI1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_EDGE_SELECTION_NUMB,0);	         
     break;	
    }

    case FC_MCSI2: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_EDGE_SELECTION_NUMB,0);	         
     break;	
    }
  }
}                
        
//---------------------------------------------------------------------
// NAME        : FRAME_COUNTER_FallingEdge
//
// DESCRIPTION : Counter works on Falling Edge 
//
// PARAMETERS  : 	FC_MCBSP1	  	or       
//             		FC_MCSI1		or       
//		        FC_MCSI2		
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void FRAME_COUNTER_FallingEdge(FRAME_COUNTER_Type Fctype)
{
 switch (Fctype)
 {
  case FC_MCBSP1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCBSP1_REG_EDGE_SELECTION_NUMB,1);	         
     break;	
    }

    case FC_MCSI1: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI1_REG_EDGE_SELECTION_NUMB,1);	         
     break;	
    }

    case FC_MCSI2: 
    {
     SetGroupBits32(FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_EDGE_SELECTION_POS, FRAME_COUNTER_CONTROL_SYNC_MCSI2_REG_EDGE_SELECTION_NUMB,1);	         
     break;	
    }
  }
}                       


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