triton_i2c.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//
// LIMITATIONS : This test works with interrupts. 
//               Transmitted datas are saved in  SDRAM_BASE_ADDR_ARM address to allow interrupt handler to go and pick them up.
//---------------------------------------------------------------------
void MSI2C_MasterIntSendAbb ( UWORD8 register_adress,
				  UWORD8 data8)
{
  UWORD16 msi2c_stat_save;
  UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
  UWORD8  data_number = 2;                 // number of byte data to tramsmit when I2c write access to Abb
  UWORD16 wait;
  UWORD16 *data_to_send_mem_int = (UWORD16 *) (SDRAM_BASE_ADDR_ARM);// pointer init

   //global variables init
  flag_transmit_end = 0;

    //enable interrupts
  //MSI2C_EnableIT(GC);   // Enable General Call interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (XRDY); // Enable Transmit data ready interrupt of the I2c bus
  //MSI2C_EnableIT(RRDY); // Enable Receive data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (ARDY); // Enable Register access ready  of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (NACK); // Enable No acknoledgment interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (AL);   // Enable Arbitration lost interrupt of the I2c bus

  data16_to_send_nb_int = 0;// pointer index init
  data_to_send_mem_int[0] = ( ((UWORD16 )register_adress) | (((UWORD16 )data8)<<8));// first transmitted half word init
     
  //configure the number of data to send
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;

  //configure slave_adress
  MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM)= slave_adress;

  wait = 0;
  //wait for bus free
  while(   (wait++ < LIMIT_CYCLENUMB) &&  ( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));
  
  // Start transmission 
  //configuration of i2c transmission : master , tranmit, no repeat, stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8603; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 1 , XA= 0 , RM = 0 , STP = 1, STT = 1

  wait = 0;
  while(( wait++ < LIMIT_CYCLENUMB  )  && (flag_transmit_end == 0) ); // wait for register access ready interrupt

  flag_transmit_end = 0;
  data16_to_send_nb_int = 0;
}

//---------------------------------------------------------------------
// NAME        : MSI2C_MasterIntReceiveAbb
//
// DESCRIPTION :  data read of one data (for 8 bits register) from Abb
//
// PARAMETERS  : UWORD8 register_adress : 7bit slave device adress (NOTE : Fill MSB bits with 0)
//              
//
// RETURN VALUE: data read
//               Error
//
// LIMITATIONS : This test works with interrupts. 
//               Transmitted datas are saved in  SDRAM_BASE_ADDR_ARM address to allow interrupt handler to go and pick them up.
//---------------------------------------------------------------------
 
UWORD8 MSI2C_MasterIntReceiveAbb(UWORD8 register_adress)
{
  UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
  UWORD16 data_number = 1;                 // number of byte data to tramsmit when I2c write access to Abb
  UWORD16 wait;
  UWORD8  ReadData8_int;
  UWORD16 *data_to_send_mem_int = (UWORD16 *) (SDRAM_BASE_ADDR_ARM);// pointer init

   //global variables init
  flag_transmit_end = 0;
  flag_receive_end = 0;

    //enable interrupts
  //MSI2C_EnableIT(GC);   // Enable General Call interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (XRDY); // Enable Transmit data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (RRDY); // Enable Receive data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (ARDY); // Enable Register access ready  of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (NACK); // Enable No acknoledgment interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (AL);   // Enable Arbitration lost interrupt of the I2c bus

  data16_to_send_nb_int = 0;// pointer index init
  data_to_send_mem_int[0] = ((UWORD16 )register_adress);// first transmitted half word init  

  //data_number 
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;

  //configure slave_adress
  MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM) = slave_adress;
 
  wait = 0;

  //wait for bus free
  while( (wait++ < LIMIT_CYCLENUMB) &&  (MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));

  // Start transmission 

  // 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write.

  //configuration of i2c transmission : master , Receive, no repeat, no stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8601; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 0, STT = 1

  wait = 0;
  while( (wait++ < LIMIT_CYCLENUMB) &&  ( flag_transmit_end == 0 ) );// wait for register access ready interrupt

  flag_transmit_end = 0;
  data16_to_send_nb_int = 0;



  // 2 nd part: read.  2 nd part: read.  2 nd part: read.  2 nd part: read.  2 nd part: read.

  //data_number 
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;

  wait = 0;

  //configuration of i2c transmission : master , Receive, no repeat, stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8403; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 1, STT = 1

  while( (wait++ < LIMIT_CYCLENUMB) &&  ( flag_receive_end == 0  ) );// wait for register access ready interrupt

  flag_receive_end = 0;
  ReadData8_int = ( (UWORD8) ReadData16_int );
  return(ReadData8_int);
} 


//---------------------------------------------------------------------
// NAME        : MSI2C_MasterIntSend_16bits_Abb
//
// DESCRIPTION : data transfert of two datas, 2 bytes (for 16 bits register) to Abb
//
// PARAMETERS  : UWORD8         register_adress  : 7bit slave device address (NOTE : Fill MSB bits with 0)
//               UWORD16         data16          : data 16 bits. 
//
// RETURN VALUE: err_none
//               err_NACK_STAT
//
// LIMITATIONS : This test works with interrupts. 
//               Transmitted datas are saved in  SDRAM_BASE_ADDR_ARM address to allow interrupt handler to go and pick them up.
//---------------------------------------------------------------------
void MSI2C_MasterIntSend_16bits_Abb ( UWORD8 register_adress,
					  UWORD16 data16)
{
  UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
  UWORD8  data_number =     3;             // number of byte data to tramsmit when I2c write access to Abb
  UWORD16 wait;
  UWORD16 *data_to_send_mem_int = (UWORD16 *) (SDRAM_BASE_ADDR_ARM);// pointer init
 
   //global variables init
  flag_transmit_end = 0;

    //enable interrupts
  //MSI2C_EnableIT(GC);   // Enable General Call interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (XRDY); // Enable Transmit data ready interrupt of the I2c bus
  //MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (RRDY); // Enable Receive data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (ARDY); // Enable Register access ready  of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (NACK); // Enable No acknoledgment interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (AL);   // Enable Arbitration lost interrupt of the I2c bus

  data16_to_send_nb_int = 0;// pointer index init
  data_to_send_mem_int [0]= ( ((UWORD16 )register_adress) | (((UWORD16 )data16)<<8));// first transmitted half word init  
  data_to_send_mem_int [1] = (((UWORD16 )data16)>>8);// second transmitted byte init  
     
  //configure the number of data to send
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;

  //configure slave_adress
  MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM)= slave_adress;

  wait = 0;
  
  //wait for bus free
  while(   (wait++ < LIMIT_CYCLENUMB) &&  ( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));

  // Start transmission 
  //configuration of i2c transmission : master , tranmit, no repeat, stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8603; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 1 , XA= 0 , RM = 0 , STP = 1, STT = 1

  wait = 0;

  while( (wait++ < LIMIT_CYCLENUMB) &&  (flag_transmit_end == 0) );// wait for register access ready interrupt
    
  data16_to_send_nb_int = 0;
  flag_transmit_end = 0;
      
  return;          

}

//---------------------------------------------------------------------
// NAME        : MSI2C_MasterIntReceive_16bits_Abb
//
// DESCRIPTION : data read of two datas (for 16 bits register) from Abb
//
// PARAMETERS  : UWORD8 register_adress : 7bit slave device adress (NOTE : Fill MSB bits with 0)
//              
//
// RETURN VALUE: data read
//               Error
//
// LIMITATIONS : This test works with interrupts. 
//               Transmitted datas are saved in  SDRAM_BASE_ADDR_ARM address to allow interrupt handler to go and pick them up.
//---------------------------------------------------------------------
UWORD16 MSI2C_MasterIntReceive_16bits_Abb(UWORD8 register_adress)
{
 
  UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
  UWORD8  data_number = 1;                 // number of byte data to tramsmit when I2c write access to Abb
  UWORD16 data16;
  UWORD16 ReadData;
  UWORD16 wait;
  UWORD16 *data_to_send_mem_int = (UWORD16 *) (SDRAM_BASE_ADDR_ARM);// pointer init

   //global variables init
  flag_transmit_end = 0;
  flag_receive_end = 0;

    //enable interrupts
  //MSI2C_EnableIT(GC);   // Enable General Call interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (XRDY); // Enable Transmit data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (RRDY); // Enable Receive data ready interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (ARDY); // Enable Register access ready  of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (NACK); // Enable No acknoledgment interrupt of the I2c bus
  MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (AL);   // Enable Arbitration lost interrupt of the I2c bus

  data16_to_send_nb_int = 0;// pointer index init
  data_to_send_mem_int[0]  = ((UWORD16 )register_adress);// first transmitted half word init  
  
  //data_number 
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;

  //configure slave_adress
  MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM) = slave_adress;
 
  // BDEC may 24 th, 2004
  wait = 0;

  //wait for bus free
  while( (wait++ < LIMIT_CYCLENUMB) &&  (MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));


  // Start transmission 

  // 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write.

  //configuration of i2c transmission : master , Receive, no repeat, no stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8601; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 0, STT = 1

  wait = 0;
  while( (wait++ < LIMIT_CYCLENUMB) &&  ( flag_transmit_end == 0 )) ;// wait for register access ready interrupt

  flag_transmit_end = 0;
  data16_to_send_nb_int = 0;


  // 2 nd part: read.  2 nd part: read.  2 nd part: read.  2 nd part: read.  2 nd part: read.
  wait = 0;

  //data_number 
  MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= 2 ;  // 16 bits = 2 bytes

  //configuration of i2c transmission : master , Receive, no repeat, stop bit and start bit
  MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8403; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 1, STT = 1
 
	 while( (wait++ < LIMIT_CYCLENUMB) &&  ( flag_receive_end == 0  ) );// wait for register access ready interrupt

  flag_receive_end = 0;
  return(ReadData16_int);
} 


//---------------------------------------------------------------------
// NAME        :  MSI2C_AccessPage
//
// DESCRIPTION : Allow to select the page where the Abb module is located
//               
//
// PARAMETERS  : the page number to access
//             
//
// RETURN VALUE: none
//              
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void MSI2C_AccessPage(const UWORD8 PageNber) 
{

  if( PageNber != Abb_page_in_use )
    {  
      MSI2C_MasterPollingSendAbb(CKG_PAGEREG, PageNber);
    }
 
  Abb_page_in_use = PageNber;


}



/***************************************************************
***** Name : MSI2C_Master_Sr_Polling_Send
***** Func : standard function for multiple I2c Device.
***** data :2005-09-19 by yubo
***************************************************************/


void MSI2C_Master_Sr_Polling_Send (UWORD16 slave_adress,
                                            UWORD16 own_adress,
                                            UWORD8 *data_array8,
                                            UWORD8 data_number)
    
	{   
	    int wait;
	    UWORD16 msi2c_stat_save,count,msi2c_iv_save;
            UWORD16 data_array16[400], *pointer_array16;
            UWORD8 i=0,last_byte,pointer_array8;
          
            for ( i = 0 ; i < (data_number>>1) ; i++ )
             {
               data_array16[i] = ( ((UWORD16 )data_array8[2*i]) | (((UWORD16 )data_array8[2*i+1])<<8));
             }
           
           if ( data_number & 0x01 ) 
             {
                last_byte = data_array8[data_number - 1];
             } 
           
           MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
           
           MSI2C_OAR(MSI2C_1_BASE_ADDR_ARM) = own_adress;
           
           MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM)= slave_adress;
           
           while( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK);
           
           pointer_array16 = &(data_array16[0]) ; 
           
           MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8603;
           
           count = 0 ;
           wait=0;
           while((wait < LIMIT_CYCLENUMB))
             { 
			    wait++;
             	if(( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
             	 {
             	   if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
             	     {
             	     	if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_XRDY_MASK) == MSI2C_STAT_XRDY_MASK)
             	     	  {
             	     	     if (  data_number - count == 1)	
             	     	        {
             	     	          MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = last_byte;	
             	     	        }
             	     	     else
             	     	        {
             	     	           MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = *pointer_array16;
             	     	           pointer_array16++;
            
                                   count += 2;	
             	     	        }   
             	     	  }
             	     	MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_XRDY_MASK; 	
             	     }
             	 }
             	
               if((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == MSI2C_STAT_ARDY_MASK)
	            {                  
	             // End of transmission 
	             MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
	             return;          
	            }
   
             	 
             }	//end while 
           
	}