📄 triton_i2c.c
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}
}
//Clear ARDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
//data_number
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
// 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read.
wait = 0;
//configuration of i2c transmission : master , Receive, no repeat, stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8403; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 1, STT = 1
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM)& MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK ) )
{
wait++;
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_RRDY_MASK) != 0x00)
{
ReadData=MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM);
//Clear RRDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_RRDY_MASK;
}
}
}
} // while
// End of transmission
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
return(ReadData);
}
UWORD8 MSI2C_MasterPollingReceive(UWORD8 DeviceAddress,UWORD8 register_adress)
{
UWORD16 slave_adress = DeviceAddress;//AbbDeviceAddress; // triton slave address
UWORD16 data_number = 1; // number of byte data to tramsmit when I2c write access to Abb
UWORD16 data16;
UWORD8 ReadData;
UWORD16 wait;
//data16 = ( ((UWORD16 )register_adress) | (((UWORD16 )data8)<<8));
data16 = ((UWORD16 )register_adress);
//data_number
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
//configure slave_adress
MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM) = slave_adress;
wait = 0;
//wait for bus free
while( (wait < LIMIT_CYCLENUMB) && (MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK))
{
wait++;
}
// Start transmission
// 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write.
//configuration of i2c transmission : master , Receive, no repeat, no stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8601; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 0, STT = 1
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK) )
{
wait++;
if(( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_XRDY_MASK) == MSI2C_STAT_XRDY_MASK)
{
MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = data16;
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_XRDY_MASK;
}
}
}
}
//Clear ARDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
//data_number
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
// 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read.
wait = 0;
//configuration of i2c transmission : master , Receive, no repeat, stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8403; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 1, STT = 1
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM)& MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK ) )
{
wait++;
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_RRDY_MASK) != 0x00)
{
ReadData=MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM);
//Clear RRDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_RRDY_MASK;
}
}
}
} // while
// End of transmission
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
return(ReadData);
}
//ahuo
//---------------------------------------------------------------------
// NAME : MSI2C_MasterPollingSend_16bits_Abb
//
// DESCRIPTION : data transfert of two datas, 2 bytes (for 16 bits register) to Abb
//
// PARAMETERS : UWORD8 register_adress : 7bit slave device address (NOTE : Fill MSB bits with 0)
// UWORD16 data16 : data 16 bits.
//
// RETURN VALUE: err_none
// err_NACK_STAT
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void MSI2C_MasterPollingSend_16bits_Abb ( UWORD8 register_adress,
UWORD16 data16)
{
UWORD16 msi2c_stat_save;
UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
UWORD8 data_number = 3; // number of byte data to tramsmit when I2c write access to Abb
UWORD16 wait;
UWORD16 count;
//configure the number of data to send
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
//configure slave_adress
MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM)= slave_adress;
wait = 0;
//wait for bus free
while( (wait < LIMIT_CYCLENUMB) && ( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));
{
wait++;
}
// Start transmission
//configuration of i2c transmission : master , tranmit, no repeat, stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8603; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 1 , XA= 0 , RM = 0 , STP = 1, STT = 1
wait = 0;
count = 0 ;
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK) )
{
wait++;
if(( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_XRDY_MASK) == MSI2C_STAT_XRDY_MASK)
{
if ( count == 0)
{
//MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = (UWORD16) register_adress ;
MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = ( ((UWORD16 )register_adress) | (((UWORD16 )data16)<<8));
count += 1;
}
else
{
MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = (((UWORD16 )data16)>>8);
}
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_XRDY_MASK;
}
}
}
} // while
if((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == MSI2C_STAT_ARDY_MASK)
{
// End of transmission
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
}
return;
}
//---------------------------------------------------------------------
// NAME : MSI2C_MasterPollingReceive_16bits_Abb
//
// DESCRIPTION : data read of two datas (for 16 bits register) from Abb
//
// PARAMETERS : UWORD8 register_adress : 7bit slave device adress (NOTE : Fill MSB bits with 0)
//
//
// RETURN VALUE: data read
// Error
//
// LIMITATIONS : None
//---------------------------------------------------------------------
UWORD16 MSI2C_MasterPollingReceive_16bits_Abb(UWORD8 register_adress)
{
UWORD16 slave_adress = AbbDeviceAddress; // triton slave address
UWORD8 data_number = 1; // number of byte data to tramsmit when I2c write access to Abb
UWORD16 data16;
UWORD16 ReadData;
UWORD16 wait;
//data16 = ( ((UWORD16 )register_adress) | (((UWORD16 )data8)<<8));
data16 = ((UWORD16 )register_adress);
//data_number
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
//configure slave_adress
MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM) = slave_adress;
// BDEC may 24 th, 2004
wait = 0;
//wait for bus free
while( (wait < LIMIT_CYCLENUMB) && (MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));
{
wait++;
}
// Start transmission
// 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write. 1 st part: write.
//configuration of i2c transmission : master , Receive, no repeat, no stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8601; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 0, STT = 1
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK) )
{
wait++;
if(( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_XRDY_MASK) == MSI2C_STAT_XRDY_MASK)
{
MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM) = data16;
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_XRDY_MASK;
}
}
}
}
//Clear ARDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
// 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read. 2 nd part: read.
wait = 0;
//data_number
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= 2 ; // 16 bits = 2 bytes
//configuration of i2c transmission : master , Receive, no repeat, stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8403; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 0 , XA= 0 , RM = 0 , STP = 1, STT = 1
while( (wait < LIMIT_CYCLENUMB) && ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM)& MSI2C_STAT_ARDY_MASK) != MSI2C_STAT_ARDY_MASK ) )
{
wait++;
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_NACK_MASK) == 0x00)
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_ARDY_MASK) == 0x00 )
{
if ((MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_RRDY_MASK) != 0x00)
{
ReadData=MSI2C_DATA(MSI2C_1_BASE_ADDR_ARM);
//Clear RRDY bit
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_RRDY_MASK;
}
}
}
} // while
// End of transmission
MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) &= MSI2C_STAT_ARDY_MASK;
return(ReadData);
}
//---------------------------------------------------------------------
// NAME : MSI2C_MasterIntSendGenCallAbb
//
// DESCRIPTION : Custom General Call access to change the Abb I2c device address of Abb
//
// PARAMETERS : UWORD8 new_device_adress : 7bit slave device address (NOTE : Fill MSB bits with 0)
//
// RETURN VALUE: err_none
// err_NACK_STAT
//
// LIMITATIONS : This test works with interrupts.
// Transmitted datas are saved in SDRAM_BASE_ADDR_ARM address to allow interrupt handler to go and pick them up.
//---------------------------------------------------------------------
void MSI2C_MasterIntSendGenCallAbb ( UWORD8 new_device_adress)
{
// UWORD16 msi2c_stat_save;
UWORD16 slave_adress = 0x00; // triton general call slave address
UWORD8 data_number = 4; // number of byte data to tramsmit when I2c write access to Abb
UWORD16 wait;
UWORD16 *data_to_send_mem_int = (UWORD16 *) (SDRAM_BASE_ADDR_ARM);// pointer init
//global variables init
flag_transmit_end = 0;
//enable interrupts
//MSI2C_EnableIT(GC); // Enable General Call interrupt of the I2c bus
MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (XRDY); // Enable Transmit data ready interrupt of the I2c bus
//MSI2C_EnableIT(RRDY); // Enable Receive data ready interrupt of the I2c bus
MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (ARDY); // Enable Register access ready of the I2c bus
MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (NACK); // Enable No acknoledgment interrupt of the I2c bus
MSI2C_IE(MSI2C_1_BASE_ADDR_ARM) |= (AL); // Enable Arbitration lost interrupt of the I2c bus
data16_to_send_nb_int = 0; // pointer index init
data_to_send_mem_int[0] = (UWORD16) AbbPartNumber; // first transmitted half word init
data_to_send_mem_int[1] = ( ((UWORD16 ) ManufacturerId ) | (((UWORD16 )new_device_adress)<<8));// second transmitted half-word init
//configure the number of data to send
MSI2C_CNT(MSI2C_1_BASE_ADDR_ARM)= data_number;
//configure slave_adress
MSI2C_SAR(MSI2C_1_BASE_ADDR_ARM)= slave_adress;
wait = 0;
//wait for bus free
while( (wait++ < LIMIT_CYCLENUMB) && ( MSI2C_STAT(MSI2C_1_BASE_ADDR_ARM) & MSI2C_STAT_BB_MASK));
// Start transmission
//configuration of i2c transmission : master , tranmit, no repeat, stop bit and start bit
MSI2C_CON(MSI2C_1_BASE_ADDR_ARM) = 0x8603; //I2C_EN=1,BE = 0,STB= 0, MST = 1 , TRX = 1 , XA= 0 , RM = 0 , STP = 1, STT = 1
wait = 0;
while(( wait++ < LIMIT_CYCLENUMB ) && (flag_transmit_end == 0) ); // wait for register access ready interrupt
flag_transmit_end = 0;
data16_to_send_nb_int = 0;
}
//---------------------------------------------------------------------
// NAME : MSI2C_MasterIntSendAbb
//
// DESCRIPTION : data transfert of one data (for 8 bits register) to Abb
//
// PARAMETERS : UWORD8 register_adress : 7bit slave device address (NOTE : Fill MSB bits with 0)
// UWORD8 data8 : data 8bits.
//
// RETURN VALUE: err_none
// err_NACK_STAT
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