boot_a9.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//
//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
//                                                                             
//   Property of Texas Instruments 
//   For  Unrestricted  Internal  Use  Only 
//   Unauthorized reproduction and/or distribution is strictly prohibited.  
//   This product is protected under copyright law and trade secret law 
//   as an unpublished work.  
//   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//   Filename       	: boot_a9.c
//
//   Description    	: Initialization of ARM925ST, Dpll and stacks
//                            
//
//
//===============================================================================
//

#include "test.h"
#include "boot_a9.h"
#include "clkrst.h"
#include "mif.h"
#include "interrupt_mapping.h"
#include "inth2.h"
#include "result.h"
#include "timer.h"
#include "configuration.h"


#define SVC_STK_SIZE 0x50
unsigned svcStack[SVC_STK_SIZE];

#define FIQ_STK_SIZE 0x50
unsigned fiqStack[FIQ_STK_SIZE];

#define IRQ_STK_SIZE 0x50
unsigned irqStack[IRQ_STK_SIZE];

#define ABORT_STK_SIZE 0x50
unsigned abortStack[ABORT_STK_SIZE];

//
//-------------------------------------------------------------------------
//-- 256 bytes of the RAM are used as a result area                      --
//-- Its first value (position 0) is the global status of all the tests  --
//-- OK  (value 1) when all the tests are OK                             --
//-- BAD (value 2) when at least one test is bad                         --
//-- NOT_TRIED (value 0) when at least one test is not tried             --
//-------------------------------------------------------------------------
//
#pragma DATA_SECTION (spy, ".spy" ) 
UWORD16 spy [ RESULT_SIZE ] ; 

extern UWORD16 result [ RESULT_SIZE ] ; 

//----------------------------------------------------------
// NAME        : BOOT_CommonInit 
// DESCRIPTION : Gather all standard initialization 
//               
// PARAMETERS  : None
//               
// RETURN VALUE:None 
//
//  LIMITATIONS : None                                  
// -----------------------------------------------------------------------------------------------
void BOOT_CommonInit ( void )
{
   
   // Set the result array
   RES_SetLocation((UWORD32)&spy);

   // Configure & Enable Rhea Abort Interrupts
   INTH2_InitLevel(PRIVATE_RHEA_ABORT_INT, INTH_IRQ, PRIVATE_RHEA_ABORT_INT, FALLING_EDGE_SENSITIVE); 
   INTH2_InitLevel(PUBLIC_RHEA_ABORT_INT, INTH_IRQ,  PUBLIC_RHEA_ABORT_INT,  FALLING_EDGE_SENSITIVE); 
   INTH2_EnableOneIt (PRIVATE_RHEA_ABORT_INT, INTH_IRQ); 
   INTH2_EnableOneIt (PUBLIC_RHEA_ABORT_INT,  INTH_IRQ); 

   // Enable abort generation on ARM public and private Rhea bridge
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PUB_EXT_ADDR) &= 0xFFFD;
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PRV_EXT_ADDR) &= 0xFFFD;
}

void BOOT_CommonInit_MMC1_USIM ( void )
{
   
   // Set the result array
   RES_SetLocation((UWORD32)&spy);

   // Configure & Enable Rhea Abort Interrupts
   INTH2_InitLevel(PRIVATE_RHEA_ABORT_INT, INTH_IRQ, PRIVATE_RHEA_ABORT_INT, FALLING_EDGE_SENSITIVE); 
   INTH2_InitLevel(PUBLIC_RHEA_ABORT_INT, INTH_IRQ,  PUBLIC_RHEA_ABORT_INT,  FALLING_EDGE_SENSITIVE); 
   INTH2_EnableOneIt (PRIVATE_RHEA_ABORT_INT, INTH_IRQ); 
   INTH2_EnableOneIt (PUBLIC_RHEA_ABORT_INT,  INTH_IRQ); 

   // Enable abort generation on ARM public and private Rhea bridge
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PUB_EXT_ADDR) &= 0xFFFD;
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PRV_EXT_ADDR) &= 0xFFFD;

   // Enable MMC_SDIO_1 and USIM PBIAS I/O

   CONFIGURATION_VOLTAGE_CTRL_0 = 0x0000002D;
   TIME_WaitUs(OSTIMER1, POLLING_MODE, 50);
   CONFIGURATION_VOLTAGE_CTRL_0 = 0x00000036;
}

//---------------------------------------------------------------------
// NAME        : set the arm in idle mode
//               
// DESCRIPTION : 
//               Set the arm in idle mode by writing in the CP15 co-proc
//               
// PARAMETERS  : None
//               
// RETURN VALUE: None
//               
// LIMITATIONS : Need to be in Supervisor mode to be able to acces the CP15 register
//               
//---------------------------------------------------------------------

void arm9_idle(void)
{
  INT_SetSupervisor();
  wait_for_interrupt();
  INT_SetUser();

}


//----------------------------------------------------------
// NAME        : Board_CommonInit 
// DESCRIPTION : Gather all standard initialization on Thalassa Board
//               
// PARAMETERS  : None
//               
// RETURN VALUE: 1 if initialization is ok, 0 else.
//
//  LIMITATIONS : None                                  
// -----------------------------------------------------------------------------------------------
int Board_CommonInit ( void )
{
   
   
   // Configure & Enable Rhea Abort Interrupts
   INTH2_InitLevel(PRIVATE_RHEA_ABORT_INT, INTH_IRQ, PRIVATE_RHEA_ABORT_INT, FALLING_EDGE_SENSITIVE); 
   INTH2_InitLevel(PUBLIC_RHEA_ABORT_INT, INTH_IRQ,  PUBLIC_RHEA_ABORT_INT,  FALLING_EDGE_SENSITIVE); 
   INTH2_EnableOneIt (PRIVATE_RHEA_ABORT_INT, INTH_IRQ); 
   INTH2_EnableOneIt (PUBLIC_RHEA_ABORT_INT,  INTH_IRQ); 

   // Enable abort generation on ARM public and private Rhea bridge
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PUB_EXT_ADDR) &= 0xFFFD;
   *(UWORD16 *) (ENHANCED_RHEA_CNTL_PRV_EXT_ADDR) &= 0xFFFD;
   
   // Lock the DPLL to 221MHz (M=17, N=1 => 17*13MHz)
   //Due to problems are slowering down to 10
   if ( !CLKRST_DpllWarmSetClockAndLock(10, 1, DPLL1) )
         return 0;
	 
   return 1;
   
}