init_cs.c
来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C语言 代码 · 共 348 行
C
348 行
/*
===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : init_cs.c
//
// Description : initialization of Chip select for several configuration
//
// Project : ARM925ST
//
// Author : Francis Huguenin fhugueni@tif.ti.com
//
===============================================================================
*/
#include "init_cs.h"
#include "intvecs.h"
#include "mem.h"
#include "arm.h"
#include "mif.h"
#include "mmu.h"
/*
--------------------------------------------------------------
NAME : INITCS_DebugConfig
DESCRIPTION : initialize the corresponding CS select
for debug configuration
PARAMETERS : CS0->CS4
RETURN VALUE: None -
LIMITATIONS : None -
--------------------------------------------------------------
*/
void INITCS_DebugConfig(CsId_t cs_id)
{
switch (cs_id)
{
case CS0:
{
/* MIF_Slow_nCS0 is already setup by intvecs.asm */
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS0,
MIF_MEMORY_32BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x1, // pgwst_welen
0x1, // write_wait_state
0x1, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_2,// clock divider
NO_FLASH_INTEL);
break;
}
case CS1:
{
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS1,
MIF_MEMORY_32BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x0F, // pgwst_welen
0x0F, // write_wait_state
0x0F, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_1,// clock divider
NO_FLASH_INTEL);
break;
}
case CS2:
{
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS2,
MIF_MEMORY_32BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x02, // pgwst_welen
0x1, // write_wait_state
0x02, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_4,// clock divider
NO_FLASH_INTEL);
break;
}
case CS3:
{ // should be not used because flash needs some specific initializations
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS3,
MIF_MEMORY_32BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x02, // pgwst_welen
0x1, // write_wait_state
0x02, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_4,// clock divider
NO_FLASH_INTEL);
break;
}
case CS4:
/* Chip Select 4 EXTERNAL FAST */
/* config for SDRAM NEC UPD4564163 1 Mo * 16 (data bits)* 4 banks */
{
MIF_InitFastInterfaceSdramConfigReg
(MIF_SELF_REFRESH_DISABLE, /* SDRAM clock is generate => SDRAM not Idle */
// MIF_SDRAM_RETIMING_ENABLE,
MIF_SDRAM_RETIMING_DISABLE,
MIF_AUTO_REFRESH_ENABLE, /* one command for refresh */
SDRAM_TYPE_64MBITS_4BANK_16DATA, // Sdram Type: 64 Megabits, 16 bits Data bus, 4 Banks
// SDRAM_TYPE_128MBITS_4BANK_16DATA, // Sdram Type: 128 Megabits, 16 bits Data bus, 4 Banks
// SDRAM_TYPE_256MBITS_4BANK_16DATA, // Sdram Type: 256 Megabits, 16 bits Data bus, 4 Banks
400, /* Auto Refresh Counter */
MIF_SDRAM_FREQ_0, /* Frequency Domain 0 */
MIF_POWER_DOWN_ENABLE,
MIF_SDRAM_CLOCK_ENABLE);
MIF_InitFastInterfaceSdramMrsReg(MIF_CAS_LATENCY_3);
break;
}
default:
break;
}
}
void INITCS_TestConfig(CsId_t cs_id)
{;}
void INITCS_Cs4MicronBoardConfig(void)
{
// Chip Select 4 EXTERNAL FAST
MIF_InitFastInterfaceSdramConfigReg
(MIF_SELF_REFRESH_DISABLE, // SDRAM clock is generate => SDRAM not Idle
MIF_SDRAM_RETIMING_DISABLE,
MIF_AUTO_REFRESH_ENABLE, // autorefresh burst length = 1
SDRAM_TYPE_128MBITS_4BANK_8DATA,
AUTO_REFRESH_COUNTER_VALUE_65_MHZ,
FREQUENCY_DOMAIN, // Frequency Domain
MIF_POWER_DOWN_DISABLE,
MIF_SDRAM_CLOCK_ENABLE);
MIF_InitFastInterfaceSdramMrsReg(MIF_CAS_LATENCY_2);
}
/*
--------------------------------------------------------------
NAME : INITCS_BoardConfig
DESCRIPTION : initialize the corresponding CS select
for board configuration
PARAMETERS : CS0->CS4
RETURN VALUE: None -
LIMITATIONS : None -
--------------------------------------------------------------
*/
void INITCS_BoardConfig(CsId_t cs_id)
{
switch (cs_id)
{
case CS0:
{
// value for strata flash Tread = 150 ns Twe= 70 ns (system clock 65 MHz)
// it can be used for a Intel burst flash (Tread = 90 ns Twrite= 75 ns)
// valueSlowConfRegCS0 .word 0x00104098
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS0,
MIF_MEMORY_16BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x05, // pgwst_welen
0x1, // write_wait_state
0x0A, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_1,// clock divider
FLASH_INTEL);
break;
}
case CS1:
{
//value for SRAM SAMSUNG-8l Tread = 85 ns Twe= 60 ns (system clock 65 MHz)
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS1,
MIF_MEMORY_16BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x04, // pgwst_welen
0x02, // write_wait_state
0x06, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_1,// clock divider
NO_FLASH_INTEL);
break;
}
case CS2:
{
break;
}
case CS3:
{
// already done normaly in intvecs.asm
// value for SRAM SAMSUNG-8l Tread = 85 ns Twe= 60 ns (system clock 65 MHz)
// It can be used for a AMD Flash AM29dl323cb-90 (Tread = 90 ns Twrite= 90 ns)
MIFTST_EmifInitSlowCSConfigReg(MIF_Slow_nCS3,
MIF_MEMORY_16BIT_WIDE,
MIF_ASYNC_READ, // read_mode
0x04, // pgwst_welen
0x02, // write_wait_state
0x06, // read_wait_state
PIPELINE_MODE, // pipeline_flowthrough
MIF_NOT_RETIMED,
MIF_DIVIDE_BY_1,// clock divider
NO_FLASH_INTEL);
break;
}
case CS4:
// Chip Select 4 EXTERNAL FAST
// PARAMATERS FOR SDRAM NEC UPD4564163 with system clock to 65 MHz
{
MIF_InitFastInterfaceSdramConfigReg
(MIF_SELF_REFRESH_DISABLE, // SDRAM clock is generate => SDRAM not Idle
// MIF_SDRAM_RETIMING_ENABLE,
MIF_SDRAM_RETIMING_DISABLE,
MIF_AUTO_REFRESH_ENABLE, // one command for refresh
SDRAM_TYPE_64MBITS_4BANK_16DATA, // Sdram Type: 64 Megabits, 16 bits Data bus, 4 Banks
// SDRAM_TYPE_128MBITS_4BANK_16DATA, // Sdram Type: 128 Megabits, 16 bits Data bus, 4 Banks
// SDRAM_TYPE_256MBITS_4BANK_16DATA, // Sdram Type: 256 Megabits, 16 bits Data bus, 4 Banks
AUTO_REFRESH_COUNTER_VALUE_65_MHZ, // Auto Refresh Counter
FREQUENCY_DOMAIN,
MIF_POWER_DOWN_ENABLE,
MIF_SDRAM_CLOCK_ENABLE);
MIF_InitFastInterfaceSdramMrsReg(MIF_CAS_LATENCY_2);
break;
}
default:
break;
}
}
void INITCS_InitTtbValidCacheForBoardConfig(void)
{
#define TTB BRD_CS4_SDRAM_TTB_ADDRESS /* Translation Table Base */
#define DOMAIN 0xFFFFFFFF /* all domains are manager */
UWORD32 i;
/*
------------------------------------------------------------
-- 3) Build Translation Table and Enable MMU, Data Cache --
-- and Instruction Cache --
------------------------------------------------------------
*/
// descriptors for nCS0
for (i = 0; i < 32; i++)
{
ARM_Section(BRD_CS0_FLASH_STRATA_0_ADDRESS + (0x00100000 * i),
BRD_CS0_FLASH_STRATA_0_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, CACHEABLE);
}
// descriptors for nCS1
for (i = 0; i < 32; i++)
{
ARM_Section(BRD_CS1_ADDRESS + (0x00100000 * i),
BRD_CS1_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, CACHEABLE);
}
/*
// descriptors for nCS2
for (i = 0; i < 32; i++)
{
ARM_Section(BRD_CS2_ADDRESS + (0x00100000 * i),
BRD_CS2_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, CACHEABLE);
}
*/
// descriptors for nCS3
// becare full with overlay mode these descriptor correspond to CS0 address
for (i = 0; i < 32; i++)
{
ARM_Section(BRD_CS3_SRAM_ADDRESS + (0x00100000 * i),
BRD_CS3_SRAM_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, CACHEABLE);
}
// descriptors for nCS4
for (i = 0; i < 2; i++)
{
ARM_Section(BRD_CS4_SDRAM_ADDRESS + (0x00100000 * i),
BRD_CS4_SDRAM_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, 0); // Non Cacheable area
}
for (i = 2; i < 8; i++)
{
ARM_Section(BRD_CS4_SDRAM_ADDRESS + (0x00100000 * i),
BRD_CS4_SDRAM_ADDRESS + (0x00100000 * i),
TTB, ALL_ACCESS, DOMAIN0, CACHEABLE);
}
// descriptors for nCS6
ARM_Section( BRD_FRAME_BUFFER_ADDRESS, BRD_FRAME_BUFFER_ADDRESS, TTB,
ALL_ACCESS, DOMAIN0, CACHEABLE);
// External and Internal Peripherals and configuration register mapping
ARM_Section( MEM_RHEA_STROBE1_ADDR, MEM_RHEA_STROBE1_ADDR,
TTB, ALL_ACCESS, DOMAIN0, 0); // Non Cacheable area
INT_SetSupervisor();
ARM_WRITE_TTBR(TTB); // Set Translation Table Base Register
ARM_WRITE_DOMAIN_REG(DOMAIN); // Set DOMAIN Accesses Control Register
// Enable IC, DC and MMU
ARM_WRITE_REG1(M_bit + C_bit + I_bit);
//ARM_WRITE_REG1(M_bit + I_bit);
INT_SetUser();
}
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