fpga_dolo.c

来自「OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI」· C语言 代码 · 共 117 行

/*===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.

   Filename             : fpga.c

   Description          : Header file for fpga board access functions

===============================================================================*/



#include "fpga_dolo.h"

//-----------------------------------------------------------------------------
//                         FPGA_test_revision_read  
//-----------------------------------------------------------------------------
UWORD16 FPGA_test_revision_read(void)
{
  return(*(REGISTER_UWORD16*)FPGA_TEST_REVISION_ADDR);
}

//-----------------------------------------------------------------------------
//                         FPGA_appli_revision_read  
//-----------------------------------------------------------------------------
UWORD16 FPGA_appli_revision_read(void)
{
  return(*(REGISTER_UWORD16*)FPGA_APPLI_REVISION_ADDR);
}

//-----------------------------------------------------------------------------
//                         FPGA_LCD_ID_read  
//-----------------------------------------------------------------------------
UWORD16 FPGA_LCD_ID_read(void)
{
  return(*(REGISTER_UWORD16*)FPGA_LCD_ID_ADDR);
}

//-----------------------------------------------------------------------------
//                         FPGA_7_segment_led_write  
//-----------------------------------------------------------------------------
void FPGA_7_segment_led_write(UWORD16 LED_NB, UWORD16 value)
{
  switch (LED_NB)
    {
     case 1:
       FPGA_write(FPGA_7_SEGMENTS_LED_1_ADDR, LED_MASK, value);
       break;       
     case 2:
       FPGA_write(FPGA_7_SEGMENTS_LED_2_ADDR, LED_MASK, value);
       break;       
     case 3:
       FPGA_write(FPGA_7_SEGMENTS_LED_3_ADDR, LED_MASK, value);
       break;       
     default: 
       break;  
    }
}

//-----------------------------------------------------------------------------
//                         FPGA_7_segment_led_read  
//-----------------------------------------------------------------------------
UWORD16 FPGA_7_segment_led_read(UWORD16 LED_NB)
{
  switch (LED_NB)
    {
     case 1:
       return (*(REGISTER_UWORD16*)FPGA_7_SEGMENTS_LED_1_ADDR);
       break;       
     case 2:
       return (*(REGISTER_UWORD16*)FPGA_7_SEGMENTS_LED_2_ADDR);
       break;       
     case 3:
       return (*(REGISTER_UWORD16*)FPGA_7_SEGMENTS_LED_3_ADDR);
       break;       
     default: 
       return 0xDEAD; 
       break;  
    }
}

//-----------------------------------------------------------------------------
//                          FPGA_write(UWORD16 value)
//-----------------------------------------------------------------------------
void FPGA_write(UWORD32 reg_add, UWORD16 reg_mask, UWORD16 reg_value)
{
 UWORD16 idx_location, value, registre;
  
  idx_location = reg_mask;
  value = (UWORD16)reg_value; 
  registre= *(REGISTER_UWORD16*)reg_add;

  while((idx_location & 0x0001) == 0)
    { 
      idx_location >>= 1; 
      value <<= 1;
    } 
 registre  &= ~reg_mask;
 registre |= ((UWORD16)value & reg_mask);
 *(REGISTER_UWORD16*)reg_add = registre;
}
//
//-----------------------------------------------------------------------------
//                         FPGA_read
//-----------------------------------------------------------------------------
UWORD16 FPGA_read(UWORD32 reg_add)
{
return (*(UWORD16*)reg_add);
}