miftest.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

/*
===============================================================================
            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
                                                                             
   Property of Texas Instruments 
   For  Unrestricted  Internal  Use  Only 
   Unauthorized reproduction and/or distribution is strictly prohibited.  
   This product is protected under copyright law and trade secret law 
   as an unpublished work.  
   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
   Filename       	: MIFTEST.c

   Description    	: Body file for the test of #include "MIF.h"ARM memory interface module

   Project        	: Satustar

   Author         	: Francois Reygagne

===============================================================================
*/

#include "test.h"
#include "global_types.h"
#include "result.h"
#include "intvecs.h"
#include "miftest.h"
#include "mem.h"

#define TC_EMIF_SLOW_IF_CONFIG_REG_BOOT_VALUE   0x00000010
//#define TC_EMIF_SLOW_CONFIG_CSX_REG_BOOT_VALUE_16   0x00001108
/*
-----------------------------------------------------------------------------
               MIFTST_CheckResetSlowCSConfigReg                            -
-----------------------------------------------------------------------------
*/   
int MIFTST_CheckResetSlowCSConfigReg(const unsigned short     CsNumber,
                                      const MIF_Slow_CS_Enum_t TabSlowCS[]) 
{
unsigned short index=0;

  /* Check reset value on all the concerned slow chip select config register */
  for (index = 0 ; index < CsNumber ; index++) 
  { 			
    RES_Set(MIF_CheckResetSlowCSConfigReg(TabSlowCS[index]));
   
  }/*endfor*/

  return RES_OK;
}

/*
------------------------------------------------------------------
            MIFTST_Execute                                      -
------------------------------------------------------------------
*/
void MIFTST_Execute(const unsigned short           CsNumber,
                     const MIFTEST_ChipSelectInfo_t ChipSelect[]) 
{
unsigned short i = 0; /* loop index variable */

/* Execute all the tests on all the concerned chip select areas */
for (i = 0 ; i < CsNumber ; i ++) 
{ 			
  RES_Set( w_8_16_32(ChipSelect[i].Addr, ChipSelect[i].Length) ); 
  RES_Set( multiple(ChipSelect[i].Addr) );
  RES_Set( str_ldr (ChipSelect[i].Addr) ); 
  RES_Set( swap    (ChipSelect [i].Addr) );
}/* endfor */

}/*-------------------- end MIFTST_Execute -----------------------------------*/


//----------------------------------------------------------
// NAME         : MIFTST_TestAccessMemory
// DESCRIPTION  : access all the memory specified by the chipSelect array
//                                       
// PARAMETERS   : The chipSelect array and its size
// RETURN VALUE : None
//               
// LIMITATIONS  : Result must be initialized
// ----------------------------------------------------------
void MIFTST_TestAccessMemory(UWORD16  CsNumber, const MIFTEST_ChipSelectInfo_t ChipSelect[]) 
{
UWORD16 i = 0,step; /* loop index variable */

/* Execute all the tests on all the concerned chip select areas */
 for (i = 0 ; i < CsNumber ; i ++) 
     {
     RES_Set(RESULT_SEPARATOR);
     step=0;
     if ( w_8_16_32(ChipSelect[i].Addr, ChipSelect[i].Length)==BAD) 
	 {
	 step|=MIF_W8_16_32_ERROR;
	 }
     
     if (multiple(ChipSelect[i].Addr)==BAD) 
	 {
	 step|=MIF_MULTIPLE_ERROR;
	 }
     
     if (str_ldr(ChipSelect[i].Addr)==BAD)
	 {
	 step|=MIF_STRLDR_ERROR;
	 }
     
     if (swap(ChipSelect [i].Addr)==BAD)
	 {
	 step|=MIF_SWAP_ERROR;
	 }
 
     if (step==0)
	 RES_Set(TEST_OK);
     else
	 RES_Set( (MIF_ERROR | step) );
    }/* endfor */

}

//----------------------------------------------------------
// NAME         : MIFTST_TestAccessMemoryAsyn
// DESCRIPTION  : access all the memory specified by the chipSelect array
//                                       
// PARAMETERS   : The chipSelect array and its size
// RETURN VALUE : None
//               
// LIMITATIONS  : Result must be initialized
// ----------------------------------------------------------
void MIFTST_TestAccessMemoryAsyn(UWORD16  CsNumber, const MIFTEST_ChipSelectInfo_t ChipSelect[]) 
{
UWORD16 i = 0,step; /* loop index variable */

/* Execute all the tests on all the concerned chip select areas */
 RES_Set(RESULT_SEPARATOR);

 for (i = 0 ; i < CsNumber ; i ++) 
     {
     step=0;
     if ( w_8_16_32(ChipSelect[i].Addr, ChipSelect[i].Length)==BAD) 
	 {
	 step|=MIF_W8_16_32_ERROR;
	 }
     
     if (str_ldr(ChipSelect[i].Addr)==BAD)
	 {
	 step|=MIF_STRLDR_ERROR;
	 }
     
     if (swap(ChipSelect [i].Addr)==BAD)
	 {
	 step|=MIF_SWAP_ERROR;
	 }
 
     if (step==0)
	 RES_Set(TEST_OK);
     else
	 RES_Set( (MIF_ERROR | step) );

     PrepareMultiple(ChipSelect[i].Addr);
    }/* endfor */

}

//----------------------------------------------------------
// NAME         : MIFTST_TestAccessMemoryBurst
// DESCRIPTION  : access all the memory specified by the chipSelect array
//                to read the data prepared in burst mode                       
// PARAMETERS   : The chipSelect array and its size
// RETURN VALUE : None
//               
// LIMITATIONS  : Result must be initialized
// ----------------------------------------------------------
void MIFTST_TestAccessMemoryBurst(UWORD16  CsNumber, const MIFTEST_ChipSelectInfo_t ChipSelect[]) 
{
UWORD16 i = 0,step; /* loop index variable */

/* Execute all the tests on all the concerned chip select areas */
 RES_Set(RESULT_SEPARATOR);
 for (i = 0 ; i < CsNumber ; i ++) 
     {

     step=0;
 
    if (ReadMultiple(ChipSelect[i].Addr)==BAD) 
	 {
	 step|=MIF_MULTIPLE_ERROR;
	 }
       
     if (step==0)
	 RES_Set(TEST_OK);
     else
	 RES_Set( (MIF_ERROR | step) );

    }/* endfor */

}

//----------------------------------------------------------
// NAME         : MIFTST_ResetAllConfigReg
// DESCRIPTION  : Test all the register at reset and store the result
//                                       
// PARAMETERS   : The slowchipSelect array and BusWidth MIF_MEMORY_16BIT_WIDE or MIF_MEMORY_32BIT_WIDE
// RETURN VALUE : None
//               
// LIMITATIONS  : Result must be initialized
// ----------------------------------------------------------
void MIFTST_ResetAllConfigReg(UWORD16 CsNumber,
                              const MIF_Slow_CS_Enum_t TabSlowCS[],
										BOOL FastCsCheckRegister,
										BOOL BusWidth,
										BOOL BootModeCs3) 
{
UWORD16 index,logresult;
UWORD32 fault_address,TempReg,ResetVal2Test;
UWORD16 TempArray[18];
UWORD16 IndexTempArray = 0;


logresult=TEST_OK;
fault_address = 0;
  TempReg=REG32(MIF_PRIORITY_IMIF_REG_ADDR_SUP)&MIF_PRIORITY_IMIF_MASK;
  TempArray[IndexTempArray++]=(UWORD16)TempReg;
  TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
  if (TempReg!=MIF_PRIORITY_IMIF_RESET_VALUE)
      {
      logresult=MIF_WRONG_RESET_VALUE;
		fault_address = MIF_PRIORITY_IMIF_REG_ADDR_SUP;
  		TempArray[IndexTempArray++]=(UWORD16)fault_address;
  		TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
      }

  TempReg=REG32(MIF_PRIORITY_EMIF_REG0_ADDR_SUP)&MIF_PRIORITY_EMIF_REG0_MASK;
  TempArray[IndexTempArray++]=(UWORD16)TempReg;
  TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
  if (TempReg!=MIF_PRIORITY_EMIF_REG0_RESET_VALUE)
      {
      logresult=MIF_WRONG_RESET_VALUE;
		fault_address = MIF_PRIORITY_EMIF_REG0_ADDR_SUP;
  		TempArray[IndexTempArray++]=(UWORD16)fault_address;
  		TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
      }

  TempReg=REG32(MIF_PRIORITY_EMIF_REG1_ADDR_SUP)&MIF_PRIORITY_EMIF_REG1_MASK;
  TempArray[IndexTempArray++]=(UWORD16)TempReg;
  TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
  if (TempReg!=MIF_PRIORITY_EMIF_REG1_RESET_VALUE)
      {
      logresult=MIF_WRONG_RESET_VALUE;
		fault_address = MIF_PRIORITY_EMIF_REG1_ADDR_SUP;
  		TempArray[IndexTempArray++]=(UWORD16)fault_address;
  		TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
      }

  TempReg=REG32(MIF_CONFIG_REG_ADDR_SUP)&MIF_CONFIG_REG_MASK;
  TempArray[IndexTempArray++]=(UWORD16)TempReg;
  TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
  if (BootModeCs3)
  	  {
	  if (TempReg!=(MIF_CONFIG_REG_RESET_VALUE | MIF_CONFREG_BM_MASK))
      	{
      	logresult=MIF_WRONG_RESET_VALUE;
			fault_address = MIF_CONFIG_REG_ADDR_SUP;
  			TempArray[IndexTempArray++]=(UWORD16)fault_address;
  			TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
      	}
	  }
	else
  	  {
	  if (TempReg!=MIF_CONFIG_REG_RESET_VALUE )
      	{
      	logresult=MIF_WRONG_RESET_VALUE;
			fault_address = MIF_CONFIG_REG_ADDR_SUP;
  			TempArray[IndexTempArray++]=(UWORD16)fault_address;
  			TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
      	}
	  }



  /* Check reset value on all the concerned slow chip select config register */
  for (index = 0 ; index < CsNumber ; index++) 
      { 			
      TempReg=MIF_MifGetConfigReg(TabSlowCS[index]) & MIF_nCSX_CONFIG_REG_MASK;
      TempArray[IndexTempArray++]=(UWORD16)TempReg;
      TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
		//for CS0 or CS3 init is different in 16bits
      if ((BusWidth==MIF_MEMORY_16BIT_WIDE) AND ((TabSlowCS[index]==0) OR (TabSlowCS[index]==3)))
         {
	  ResetVal2Test=MIF_nCSX_CONFIG_REG_RESET_VALUE_16;
         }
      else
         {
         ResetVal2Test=MIF_nCSX_CONFIG_REG_RESET_VALUE_32;
         }

      if (TempReg!=ResetVal2Test)
         {
         logresult=MIF_WRONG_RESET_VALUE;
			fault_address = TabSlowCS[index];
  			TempArray[IndexTempArray++]=(UWORD16)fault_address;
  			TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
         }
      }/*endfor*/


	if (FastCsCheckRegister)
		{
		TempReg=REG32(MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP)&MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_MASK;
		TempArray[IndexTempArray++]=(UWORD16)TempReg;
		TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
		if (TempReg!=MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_RESET_VALUE)
			 {
			 logresult=MIF_WRONG_RESET_VALUE;
   		 fault_address = MIF_FAST_INTERFACE_SDRAM_CONFIG_REG_ADDR_SUP;
  			 TempArray[IndexTempArray++]=(UWORD16)fault_address;
  			 TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
			 }

		TempReg=REG32(MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP)&MIF_FAST_INTERFACE_SDRAM_MRS_MASK;
		TempArray[IndexTempArray++]=(UWORD16)TempReg;
		TempArray[IndexTempArray++]=(UWORD16)(TempReg>>16);
		if (TempReg!=MIF_FAST_INTERFACE_SDRAM_MRS_RESET_VALUE)
			 {
			 logresult=MIF_WRONG_RESET_VALUE;
   		 fault_address = MIF_FAST_INTERFACE_SDRAM_MRS_REG_ADDR_SUP;
  			 TempArray[IndexTempArray++]=(UWORD16)fault_address;
  			 TempArray[IndexTempArray++]=(UWORD16)(fault_address>>16);
			 }
		}

  ClearBit(REG32(MIF_nCS1_CONFIG_REG_ADDR_SUP),MIF_BW_MSK);

  RES_Set(RESULT_SEPARATOR);
  RES_Set(START_ARRAY_DATA);
  for (index = 0 ; index < IndexTempArray ; index++) 
      { 
	   RES_Set(TempArray[index]);
      }
  RES_Set(END_ARRAY_DATA);

  RES_Set(logresult);

}

BOOL MIFTST_PatternMemtest(UWORD32 start_address, UWORD32 size_in_byte, UWORD8 access_type)
{
#define NB_PATTERN	4
const UWORD16 pattern8[NB_PATTERN]= {0xAA,0x55,0xFF,0x00};
const UWORD16 pattern16[NB_PATTERN]= {0xAAAA,0x5555,0xFFFF,0x0000};
const UWORD32 pattern32[NB_PATTERN]= {0xAAAAAAAA,0x55555555,0xFFFFFFFF,0x00000000};

volatile UWORD32 * ptr32;
volatile UWORD16 * ptr16;
volatile UWORD8 *  ptr8;
UWORD32 i,j;
j=0;
switch (access_type)
	{
	case 8 :
		{
		 ptr8 = (UWORD8 *) start_address;
		 for (i=0; i < (size_in_byte ) ; i++)
			 {
			 *ptr8 = pattern8[j];
			 if (*ptr8 != pattern8[j])	
				 return(False);
			 ptr8++;
			 j = (j+1) % NB_PATTERN ;
			 }
		break;
		}

	case 16 :
		{
		 ptr16 = (UWORD16 *) start_address;
		 for (i=0; i < (size_in_byte /2) ; i++)
			 {
			 *ptr16 = pattern16[j];
			 if (*ptr16 !=pattern16[j])	
				 return(False);
			 ptr16++;
			 j = (j+1) % NB_PATTERN ;
			 }
		break;
		}

	case 32 :
	default :
		{
		 ptr32 = (UWORD32 *) start_address;
		 for (i=0; i < (size_in_byte /4) ; i++)
			 {
			 *ptr32 = pattern32[j];
			 if (*ptr32 != pattern32[j])	
				 return(False);
			 ptr32++;
			 j = (j+1) % NB_PATTERN ;
			 }
		break;
		}

	}
return(True);
}



BOOL MIFTST_LinearMemtest(UWORD32 start_address, UWORD32 size_in_byte, UWORD8 access_type)
{
volatile UWORD32 * ptr32;
volatile UWORD16 * ptr16;
volatile UWORD8 *  ptr8;
UWORD32 i;

switch (access_type)
	{
	case 8 :
		{
		// fill memory
		 ptr8 = (UWORD8 *) start_address;
		 for (i=0; i < (size_in_byte ) ; i++)
			 {
			 *ptr8 = (UWORD8) i;
			 ptr8++;
			 }
		// read back
		 ptr8 = (UWORD8 *) start_address;
		 for (i=0; i < (size_in_byte ) ; i++)
			 {
			 if (*ptr8 != (UWORD8) i)	
				 return(False);
			 ptr8++;
			 }
		break;
		}

	case 16 :
		{
		// fill memory
		 ptr16 = (UWORD16 *) start_address;
		 for (i=0; i < (size_in_byte /2) ; i++)
			 {
			 *ptr16 = (UWORD16) (i % 65530);
			 ptr16++;
			 }
		// read back
		 ptr16 = (UWORD16 *) start_address;
		 for (i=0; i < (size_in_byte /2) ; i++)
			 {
			 if (*ptr16 !=(UWORD16) (i % 65530))	
				 return(False);
			 ptr16++;
			 }
		break;
		}

	case 32 :
	default :
		{
		 ptr32 = (UWORD32 *) start_address;
		 for (i=0; i < (size_in_byte /4) ; i++)
			 {
			 *ptr32 = (UWORD32)i;
			 ptr32++;
			 }
		// read back
		 ptr32 = (UWORD32 *) start_address;
		 for (i=0; i < (size_in_byte /4) ; i++)
			 {
			 if (*ptr32 != (UWORD32)i)	
				 return(False);
			 ptr32++;
			 }
		break;
		}
	}
return(True);
}