msi2c.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  //--> set own address
  SetGroupBits16(MSI2C_I2C_OA_16_0(msi2c_base_address),0,10, OwnAddress);

  //--> enable module
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x8080;

  while(MSI2C_I2C_SYSS_16_0(msi2c_base_address) != 1);  // Wait reset-done

  //--> set  Slave address
  SetGroupBits16(MSI2C_I2C_SA_16_0(msi2c_base_address),0,10, SlaveAddress);

  //--> setup NbOfBytes bytes transfer
  SetGroupBits16(MSI2C_I2C_CNT_16_0(msi2c_base_address),0,16, NbOfBytes);

  //==> enable RRDY + ARDY + AL interrupts
  SetGroupBits16(MSI2C_I2C_IE_16_0(msi2c_base_address),0,6,0x0D);

  //--> Slave RX 
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,0);
}


//---------------------------------------------------------------------
// NAME        : MSI2C_ConfDmaRxMaster
//
// DESCRIPTION : Configures MSI2C for Rx DMA data transfer
//
// PARAMETERS  : MSI2C base address,  Own Address, Slave Address, Number of Bytes to receive
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_ConfDmaRxMaster(UWORD32 msi2c_base_address,  UWORD16 OwnAddress, UWORD16 SlaveAddress, UWORD16 NbOfBytes)
{
  MSI2C_reset(msi2c_base_address); 
  
  //--> set own address
  SetGroupBits16(MSI2C_I2C_OA_16_0(msi2c_base_address),0,10, OwnAddress);
  
  //--> enable module 
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x8000;
  while(MSI2C_I2C_SYSS_16_0(msi2c_base_address) != 1);           // Wait reset-done
     
  //--> set  Slave address
  SetGroupBits16(MSI2C_I2C_SA_16_0(msi2c_base_address),0,10, SlaveAddress);
  
  //--> setup NbOfBytes bytes transfer 
  SetGroupBits16(MSI2C_I2C_CNT_16_0(msi2c_base_address),0,16, NbOfBytes); 
 
  //--> enable XDMA interrupt 
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),7,1,0);  
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),15,1,1);  

 //--> enable only ARDY interrupt
  SetGroupBits16(MSI2C_I2C_IE_16_0(msi2c_base_address),0,6,4);
  
  //--> master RX 
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,2);  

}


//---------------------------------------------------------------------
// NAME        : MSI2C_StartDmaRxMaster
//
// DESCRIPTION : MSI2C Rx DMA transfer
//
// PARAMETERS  : MSI2C base address
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_StartDmaRxMaster(UWORD32 msi2c_base_address)
{
  while(GetGroupBits16(MSI2C_I2C_STAT_16_0(msi2c_base_address), 12, 1) != 0);  // Wait BB = 0

  //--> master RX 
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,2);  

  I2C_Ardy = False;

  // start transmission	
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x0003;

  // wait Access Ready Interrupt
  while (I2C_Ardy != True);
}



//---------------------------------------------------------------------
// NAME        : MSI2C_ConfDmaTxMaster
//
// DESCRIPTION : Configures MSI2C for Tx DMA data transfer
//
// PARAMETERS  : MSI2C base address,  Own Address, Slave Address, Number of Bytes to transmit
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_ConfDmaTxMaster(UWORD32 msi2c_base_address,  UWORD16 OwnAddress, UWORD16 SlaveAddress, UWORD16 NbOfBytes)
{
  MSI2C_reset(msi2c_base_address); 

  //--> set own address
  SetGroupBits16(MSI2C_I2C_OA_16_0(msi2c_base_address),0,10, OwnAddress);
  
  //--> enable module 
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x8000;
  while(MSI2C_I2C_SYSS_16_0(msi2c_base_address) != 1);  // Wait reset-done
     
  //--> set  Slave address
  SetGroupBits16(MSI2C_I2C_SA_16_0(msi2c_base_address),0,10, SlaveAddress);
  
  //--> setup NbOfBytes bytes transfer 
  SetGroupBits16(MSI2C_I2C_CNT_16_0(msi2c_base_address),0,16, NbOfBytes); 
 
  //==> enable XDMA interrupt 
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),15,1,0);  
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),7,1,1); 

   //==> enable ARDY interrupt 
  SetGroupBits16(MSI2C_I2C_IE_16_0(msi2c_base_address),0,6,4);
 
  //--> master TX 
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,3); 
}


//---------------------------------------------------------------------
// NAME        : MSI2C_StartDmaTxMaster
//
// DESCRIPTION : MSI2C Tx DMA transfer
//
// PARAMETERS  : MSI2C base address
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_StartDmaTxMaster(UWORD32 msi2c_base_address)
{
  while(GetGroupBits16(MSI2C_I2C_STAT_16_0(msi2c_base_address), 12, 1) != 0);  // Wait BB = 0

  //--> master TX 
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,3); 

  I2C_Ardy = False;

  // start transmission	
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x0003;

  // wait Access Ready Interrupt
  while (I2C_Ardy != True);

}


//---------------------------------------------------------------------
// NAME        : MSI2C_ConfDmaTxSlave
//
// DESCRIPTION : Configures MSI2C for Slave Tx DMA data transfer
//
// PARAMETERS  : MSI2C base address,  Own Address, Slave Address, Number of Bytes to transmit
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_ConfDmaTxSlave(UWORD32 msi2c_base_address,  UWORD16 OwnAddress, UWORD16 SlaveAddress, UWORD16 NbOfBytes)
{
  MSI2C_reset(msi2c_base_address);

  //--> set own address
  SetGroupBits16(MSI2C_I2C_OA_16_0(msi2c_base_address),0,10, OwnAddress);

  //--> enable module
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x8000;
  while(MSI2C_I2C_SYSS_16_0(msi2c_base_address) != 1);  // Wait reset-done

  //--> set  Slave address
  SetGroupBits16(MSI2C_I2C_SA_16_0(msi2c_base_address),0,10, SlaveAddress);

  //--> setup NbOfBytes bytes transfer
  SetGroupBits16(MSI2C_I2C_CNT_16_0(msi2c_base_address),0,16, NbOfBytes);

  //==> enable DMA Transmit interrupt
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),15,1,0);
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),7,1,1);

  //==> enable ARDY interrupt
  SetGroupBits16(MSI2C_I2C_IE_16_0(msi2c_base_address),0,6,4); 

  //--> Slave TX
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,1);
}

//---------------------------------------------------------------------
// NAME        : MSI2C_ConfDmaRxSlave
//
// DESCRIPTION : Configures MSI2C for Slave Rx DMA data transfer
//
// PARAMETERS  : MSI2C base address, Own Address, Slave Address, Number of Bytes to transmit
//
// RETURN VALUE: None
//
// LIMITATIONS : 
//---------------------------------------------------------------------

void MSI2C_ConfDmaRxSlave(UWORD32 msi2c_base_address,  UWORD16 OwnAddress, UWORD16 SlaveAddress, UWORD16 NbOfBytes)
{
  MSI2C_reset(msi2c_base_address);

  //--> set own address
  SetGroupBits16(MSI2C_I2C_OA_16_0(msi2c_base_address),0,10, OwnAddress);

  //--> enable module
  MSI2C_I2C_CON_16_0(msi2c_base_address) |= 0x8000;
  while(MSI2C_I2C_SYSS_16_0(msi2c_base_address) != 1);  // Wait reset-done

  //--> set  Slave address
  SetGroupBits16(MSI2C_I2C_SA_16_0(msi2c_base_address),0,10, SlaveAddress);

  //--> setup NbOfBytes bytes transfer
  SetGroupBits16(MSI2C_I2C_CNT_16_0(msi2c_base_address),0,16, NbOfBytes);

  //==> enable DMA Receive interrupt
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),15,1,1);
  SetGroupBits16(MSI2C_I2C_BUF_16_0(msi2c_base_address),7,1,0);

  //==> enable ARDY interrupt
  SetGroupBits16(MSI2C_I2C_IE_16_0(msi2c_base_address),0,6,4); 

  //--> Slave RX
  SetGroupBits16(MSI2C_I2C_CON_16_0(msi2c_base_address),9,2,0);
}


//---------------------------------------------------------------------
// NAME        : InitializeMemory
//
// DESCRIPTION : Writes some data into the RAM.
//
// PARAMETERS  : Tx Memory pointer, Rx Memory pointer, Number of words to write, Seed (first data)
//
// RETURN VALUE: None
//
// LIMITATIONS : Seed must be max. 0x7FFF
//---------------------------------------------------------------------

void InitializeMemory(UWORD16 * memory_tx_ptr, UWORD16 * memory_rx_ptr, UWORD16 NbOfWords, UWORD16 seed)
{ 
  register int index;
  UWORD16 * TransmitDataIndex = memory_tx_ptr;
  UWORD16 * ReceiveDataIndex = memory_rx_ptr;

  for (index = 0; index < NbOfWords; index++)
  {
    *TransmitDataIndex = seed + ((index * 0x2222)%0x7FFF);
    *ReceiveDataIndex  = 0x0;
    TransmitDataIndex++;
    ReceiveDataIndex++;
  }
}


//---------------------------------------------------------------------
// NAME        : CheckMemory
//
// DESCRIPTION : Compares the data between two RAM locations (one location
//               is used for transmit data and the other for the received data
//               for interrupt or DMA transfers using the I2C BFM). The BFM will
//               be configured to transmit the received data.
//
// PARAMETERS  : Tx memory pointer, Rx memory pointer, Number of bytes to compare
//
// RETURN VALUE: 0 if check successfull, else 1
//
// LIMITATIONS : Number of bytes to transmit can be max. 272
//---------------------------------------------------------------------

UWORD16 CheckMemory(UWORD16 * memory_tx_ptr, UWORD16 * memory_rx_ptr, UWORD16 NbOfWords)
{
  register int index = 0;
  UWORD16 * TransmitDataIndex = memory_tx_ptr;
  UWORD16 * ReceiveDataIndex = memory_rx_ptr;

  index=0;
  while ( index < NbOfWords )
  {
    if (*TransmitDataIndex != *ReceiveDataIndex)
       return(1);

    TransmitDataIndex++;
    ReceiveDataIndex++;
    index++;
  }

  return(0);
}