mcbsp2.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//===============================================================================
//            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
//   Property of Texas Instruments
//   For  Unrestricted  Internal  Use  Only
//   Unauthorized reproduction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work.
//   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
//
//
//   Filename       	: mcbsp2.c
//
//   Description    	: Header of the library driving the GPIOs
//
//   Project        	: Perseus2
//
//   Author         	: C. blanc
//
//
//===============================================================================

#include "mcbsp2.h"



/*-----------------------------------------------------------------------
 NAME        : MCBSP_LoadField						-
 DESCRIPTION : load bit field in 16 bit register			-
 SYNOPSYS    : void MCBSP_LoadField(register_addr,size,name,value)		-
 PARAMETERS  : name param is the msb position of the field to load	-
 RETURN VALUE: None.						-
 LIMITATIONS : None.						-
------------------------------------------------------------------------*/
void MCBSP2_LoadField(UWORD32 register_addr,UWORD8 size,UWORD8 name,UWORD16 value)
{
UWORD16 read = REG16(register_addr);
UWORD16 mask1 = 0x00;
UWORD16 mask2 = 0x00;

mask1 = value<<(name-size+1);
mask2 = (UWORD16) (~(((1<<size)-1)<< ((name+1)-size)));
REG16(register_addr) = (read & mask2)|mask1;
}

/*-----------------------------------------------------------------------
 NAME        : MCBSP_read_field					    	 -
 DESCRIPTION : read bit field value in 16 bit register		 -
 SYNOPSYS    : void MCBSP_LoadField(register_addr,size,name)	 	 -
 PARAMETERS  : name param is the msb position of the read field	 -
 RETURN VALUE: bit field value					 -
 LIMITATIONS : None.						 -
------------------------------------------------------------------------*/
UWORD8 MCBSP2_ReadField(UWORD32 register_addr,UWORD8 size,UWORD8 name)
{
UWORD16 read = REG16(register_addr);
return (read & (((1<<size)-1)<<((name+1)-size)))>> ((name+1)-size);
}


/*-----------------------------------------------------------------------
 NAME        : MCBSP2_TestResetValue					    	 -
 DESCRIPTION : Tests all bits register
 SYNOPSYS    : void MCBSP_TestResetValue(void)
 PARAMETERS  : None
 RETURN VALUE: None
 LIMITATIONS : None.						 -
------------------------------------------------------------------------*/
void MCBSP2_TestResetValue(void)
{
  CLKRST_SetPeripheralClockEnable(PER_CK,ENABLE);
//  CLKRST_CLKA_SetClockDivider(PER_DIV,0);
  MCBSP_SET_GROUP_BITS16(REG16(MCBSP2_MCBSP_SRGR2_REG),CLKSM,CLKSM_SZ,1);


  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,FREE);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,SOFT);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,FRST);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,GRST);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,XINTM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,XSYNCERR);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,XEMPTY);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,XRDY);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR2_REG,XRST);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,DLB);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RJUST);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,CLKSTP);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,DXENA);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,ABIS);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RINTM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RSYNCERR);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RFULL);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RRDY);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SPCR1_REG,RRST);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RPHASE);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RFRLEN2);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RWDLEN2);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RCOMPAND);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RFIG);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR2_REG,RDATDLY);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR1_REG,RFRLEN1);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_RCR1_REG,RWDLEN1);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XPHASE);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XFRLEN2);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XWDLEN2);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XCOMPAND);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XFIG);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR2_REG,XDATDLY);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR1_REG,XFRLEN1);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_XCR1_REG,XWDLEN1);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SRGR2_REG,GSYNC);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SRGR2_REG,CLKSP);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SRGR2_REG,FSGM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SRGR2_REG,FPER);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_SRGR1_REG,FWID);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR1_REG,RPBBLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR1_REG,RPABLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR1_REG,RCBLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR1_REG,RMCM);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR2_REG,XPBBLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR2_REG,XPABLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR2_REG,XCBLK);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_MCR2_REG,XMCM);

  TEST_REGISTER_RESET_VALUE(MCBSP2_MCBSP_RCERA_REG);
  TEST_REGISTER_RESET_VALUE(MCBSP2_MCBSP_RCERB_REG);
  TEST_REGISTER_RESET_VALUE(MCBSP2_MCBSP_XCERA_REG);
  TEST_REGISTER_RESET_VALUE(MCBSP2_MCBSP_XCERB_REG);

  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,XIOEN);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,RIOEN);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,FSXM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,FSRM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,CLKXM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,CLKRM);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,CLKS_STAT);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,DX_STAT);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,DR_STAT);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,FSXP);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,FSRP);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,CLKXP);
  MCBSP_TEST_FIELD_RESET_VALUE(MCBSP2_MCBSP_PCR_REG,CLKRP);


  PRINT_CURRENT_ERROR_STATUS(MCBSP_TEST_RESET_VALUE_SUCCEEDED);
}

void MCBSP2_TestRegistersAccess(void)
{
  CLKRST_SetPeripheralClockEnable(PER_CK,ENABLE);
//  CLKRST_CLKA_SetClockDivider(PER_DIV,0);
  MCBSP_SET_GROUP_BITS16(REG16(MCBSP2_MCBSP_SRGR2_REG),CLKSM,CLKSM_SZ,1);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RPHASE);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RFRLEN2);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RWDLEN2);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RCOMPAND);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RFIG);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR2_REG,RDATDLY);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR1_REG,RFRLEN1);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_RCR1_REG,RWDLEN1);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XPHASE);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XFRLEN2);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XWDLEN2);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XCOMPAND);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XFIG);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR2_REG,XDATDLY);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR1_REG,XFRLEN1);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_XCR1_REG,XWDLEN1);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR2_REG,GSYNC);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR2_REG,CLKSP);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR2_REG,CLKSM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR2_REG,FSGM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR2_REG,FPER);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR1_REG,FWID);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SRGR1_REG,CLKGDV);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR1_REG,RPBBLK);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR1_REG,RPABLK);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR1_REG,RMCM);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR2_REG,XPBBLK);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR2_REG,XPABLK);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_MCR2_REG,XMCM);

  MODIFY_REGISTER_RESET_VALUE16(MCBSP2_MCBSP_RCERA_REG);
  MODIFY_REGISTER_RESET_VALUE16(MCBSP2_MCBSP_RCERB_REG);
  MODIFY_REGISTER_RESET_VALUE16(MCBSP2_MCBSP_XCERA_REG);
  MODIFY_REGISTER_RESET_VALUE16(MCBSP2_MCBSP_XCERB_REG);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,XIOEN);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,RIOEN);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,FSXM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,FSRM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,CLKXM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,CLKRM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,DX_STAT);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,FSXP);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,FSRP);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,CLKXP);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_PCR_REG,CLKRP);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,XRST);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,RRST);

  MCBSP_SET_GROUP_BITS16(REG16(MCBSP2_MCBSP_SPCR2_REG),XRST,XRST_SZ,1);
  MCBSP_SET_GROUP_BITS16(REG16(MCBSP2_MCBSP_SPCR1_REG),RRST,RRST_SZ,1);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,FREE);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,SOFT);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,GRST);
  MCBSP_SET_GROUP_BITS16(REG16(MCBSP2_MCBSP_SPCR2_REG),GRST,GRST_SZ,1);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,FRST);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,XINTM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR2_REG,XSYNCERR);

  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,DLB);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,RJUST);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,CLKSTP);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,DXENA);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,ABIS);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,RINTM);
  MCBSP_MODIFY_FIELD_RESET_VALUE16(MCBSP2_MCBSP_SPCR1_REG,RSYNCERR);

  PRINT_CURRENT_ERROR_STATUS(MCBSP_TEST_REGISTER_ACCESS_SUCCEEDED);
}


//---------------------------------------------------------------------------
// NAME        : MCBSP2_SetPinControlRegister
// DESCRIPTION : Configure McBSP Interface pin to the dedicated configuration
// RETURN VALUE: None
// LIMITATIONS : None
//---------------------------------------------------------------------------
void  MCBSP2_SetPinControlRegister(MCBSP_ClkPol_t RXClkPol,
                                  MCBSP_ClkPol_t TXClkPol,
                                  MCBSP_FSActive_t RXFSActive,
                                  MCBSP_FSActive_t TXFSActive,
                                  MCBSP_ClockMode_t RXClockMode,
                                  MCBSP_ClockMode_t TXClockMode,
                                  MCBSP_FSSync_t RXFSSync,
                                  MCBSP_FSSync_t TXFSSync,
                                  MCBSP_GPIOInput_t RXPin,
                                  MCBSP_GPIOInput_t TXPin)
{
// Read the Pin Control Register
UWORD16 value = REG16(MCBSP2_MCBSP_PCR_REG);

// Clear all bits
value = 0;

// Set all bits
value |= RXClkPol << (CLKRP - CLKRP_SZ + 1);
value |= TXClkPol << (CLKXP - CLKXP_SZ + 1);
value |= RXFSActive << (FSRP - FSRP_SZ + 1);
value |= TXFSActive << (FSXP - FSXP_SZ + 1);
value |= RXClockMode << (CLKRM - CLKRM_SZ + 1);
value |= TXClockMode << (CLKXM - CLKXM_SZ + 1);
value |= RXFSSync << (FSRM - FSRM_SZ + 1);
value |= TXFSSync << (FSXM - FSXM_SZ + 1);
value |= RXPin << (RIOEN - RIOEN_SZ + 1);
value |= TXPin << (XIOEN - XIOEN_SZ + 1);

// Write the Pin Control Register
REG16(MCBSP2_MCBSP_PCR_REG) = value;
}