📄 flashintel.c
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//===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : Flashintel.c
//
// Description : functions for Intel burst and strata flash
//
// Project : TI925MM
//
// Author : Daniel BLANC
// Adapted by : Francis HUGUENIN
//
//===============================================================================
#include "mem.h"
#include "mif.h"
#include "flashintel.h"
#include "result.h"
//---------------------------------------------------------------------
// NAME : FLASH_lashIntelPairSetupRead
//
// DESCRIPTION : Setup the protocol in which the flash pair is read
//
// SYNOPSYS : void FLASH_lashIntelPairSetupRead(UWORD32 Address,
// BOOL intel_read_mode,
// BOOL data_hold,
// BOOL wait_delay,
// BOOL burst_mode,
// BOOL start_edge,
// Burst_length_t burst_length)
//
//
// PARAMETERS : Address, Base Address of the flash package
// intel_read_mode SYNCHRONOUS_BURST or PAGE_MODE
// code_frequency
// FC_CODE2
// FC_CODE3
// FC_CODE4
// FC_CODE5
// FC_CODE6
//
// data_hold, HOLD_DATA_ONE_CLOCK or HOLD_DATA_TWO_CLOCK
// wait_delay, WAIT_ONE_DELAY or WAIT_TWO_DELAY
// burst_mode, INTEL_BURST or LINEAR_BURST
// start_edge, BURST_START_FALLEDGE or BURST_START_RISEDGE
// burst_length, WORD_BURST_4, WORD_BURST_8 or CONTINUOUS_BURST
//
// RETURN VALUE: None
//
// LIMITATIONS : Use only for Intel burst Flash flash
//---------------------------------------------------------------------
void FLASH_lashIntelPairSetupRead(UWORD32 Address,
BOOL intel_read_mode,
UWORD8 code_frequency,
BOOL data_hold,
BOOL wait_delay,
BOOL burst_mode,
BOOL start_edge,
Burst_length_t burst_length)
{
UWORD32 RCD=0,i ; /* Configuration Register Definition */
UWORD32 Address1;
// Undefined address should be within the device
Address1 = FPAIR_UNDEFINEDADDRESS1 | Address;
// Build Register Configuration Definition Under 32 bits
RCD |= (intel_read_mode << 15);//RM
RCD |= (code_frequency << 11);//FC
RCD |= (data_hold <<9);//DOC
RCD |= (wait_delay << 8);//WC
RCD |= (burst_mode << 7);//BS
RCD |= (start_edge << 6);//CC
RCD |= (burst_length);//BL2-0
// the flash packages are connected to the arm bus from A2 to A21
// so we have to shift the address register
RCD <<= 2;
// Authorize the flash write
MIF_MifSetWriteProtect((BOOL)WRITE_AUTHORIZED);
// Set the voltage of the pin Vpp of the flash
FLASH_SetFlashProgrammVoltage((BOOL)PROGRAM_LEVEL);
// loop to wait a while
for (i=0;i<10; i++) ;
// Write the Configuration Register
WriteFlashPairRegister(Address1,FPAIR_SETREADCONF,(Address1+RCD),FPAIR_CONFIRMSETUP);
// loop to wait a while
for (i=0;i<10; i++) ;
// Forbid the flash write
MIF_MifSetWriteProtect((BOOL)WRITE_FORBIDEN);
// Set the voltage of the pin Vpp of the flash
FLASH_SetFlashProgrammVoltage((BOOL)PROTECT_LEVEL);
}
//---------------------------------------------------------------------
// NAME : FLASH_FlashIntelSetupRead
//
// DESCRIPTION : Setup the protocol in which the flash pair is read
//
// SYNOPSYS : void FLASH_lashIntelPairSetupRead(UWORD32 Address,
// BOOL intel_read_mode,
// BOOL data_hold,
// BOOL wait_delay,
// BOOL burst_mode,
// BOOL start_edge,
// Burst_length_t burst_length)
//
//
// PARAMETERS : Address, Base Address of the flash package
// intel_read_mode SYNCHRONOUS_BURST or PAGE_MODE
// code_frequency
// FC_CODE2
// FC_CODE3
// FC_CODE4
// FC_CODE5
// FC_CODE6
//
// data_hold, HOLD_DATA_ONE_CLOCK or HOLD_DATA_TWO_CLOCK
// wait_delay, WAIT_ONE_DELAY or WAIT_TWO_DELAY
// burst_mode, INTEL_BURST or LINEAR_BURST
// start_edge, BURST_START_FALLEDGE or BURST_START_RISEDGE
// burst_length, WORD_BURST_4, WORD_BURST_8 or CONTINUOUS_BURST
//
// RETURN VALUE: None
//
// LIMITATIONS : Use only for Intel burst Flash flash
//---------------------------------------------------------------------
void FLASH_FlashIntelSetupRead(UWORD32 Address,
BOOL intel_read_mode,
UWORD8 code_frequency,
BOOL data_hold,
BOOL wait_delay,
BOOL burst_mode,
BOOL start_edge,
Burst_length_t burst_length)
{
UWORD32 RCD=0 ; /* Configuration Register Definition */
// Build Register Configuration Definition Under 32 bits
RCD |= (intel_read_mode << 15);//RM
RCD |= (code_frequency << 11);//FC
RCD |= (data_hold <<9);//DOC
RCD |= (wait_delay << 8);//WC
RCD |= (burst_mode << 7);//BS
RCD |= (start_edge << 6);//CC
RCD |= (burst_length);//BL2-0
// the flash packages are connected to the arm bus from A1 to A20
// so we have to shift the address register
RCD <<= 1;
// Write the Configuration Register
WriteFlashRegister(Address,FLASH_SETREADCONF,(Address+RCD),FLASH_CONFIRMSETUP);
}
//---------------------------------------------------------------------
// NAME : FLASH_StrataFlashIntelSetupRead
//
// DESCRIPTION : Configure strata flash mode read (asynchronous or page mode)
//
// PARAMETERS : Address, Base Address of the flash package
// PageModeReadEnable: True if enable page mode read
// : False asynchronous read
// RETURN VALUE: None
//
// LIMITATIONS : Use only for strata flash
//---------------------------------------------------------------------
void FLASH_StrataFlashIntelSetupRead(UWORD32 Address,
BOOL PageModeReadEnable)
{
UWORD32 RCD; /* Configuration Register Definition */
// Build Register Configuration Definition
// Bit 15 =1 Page mode read enable
// Bit 15 =0 standard read
if (PageModeReadEnable)
RCD = 0x8000;
else
RCD = 0;
// Rcd value should be placed on address bus from A1 to A16
// so shift address
RCD = RCD << 1;
// Write the Configuration Register
WriteFlashRegister(Address,FLASH_SETREADCONF,(Address+RCD),FLASH_CONFIRMSETUP);
}
//---------------------------------------------------------------------
// NAME : FLASH_FlashIntelReadPairStatus
//
// DESCRIPTION : Get the status register of the flash
//
// SYNOPSYS : UWORD32 FLASH_FlashIntelReadPairStatus (UWORD32 Address)
//
//
// PARAMETERS : Address, Base Address of the flash package
//
// RETURN VALUE: UWORD32 the half MSB contains the status of the MSB flash package
// the half LSB contains the status of the LSB flash package
//
// LIMITATIONS : Setup the MIF block before access to flash
//---------------------------------------------------------------------
UWORD32 FLASH_FlashIntelReadPairStatus (UWORD32 Address)
{
UWORD32 Status;
UWORD32 Address1,Address2;
/* Undefined address should be within the device */
Address1 = FPAIR_UNDEFINEDADDRESS1 | Address;
Address2 = FPAIR_UNDEFINEDADDRESS2 | Address;
// Read the value of the status register
Status=ReadFlashPairRegister(Address1,FPAIR_READSTATUSDATA,Address2);
/* Read Array command to terminate operation */
REG32(Address1) = FPAIR_READARRAYDATA;
return Status;
}
//---------------------------------------------------------------------
// NAME : FLASH_FlashIntelReadStatus
//
// DESCRIPTION : Get the status register of the flash
//
// SYNOPSYS : UWORD16 FLASH_FlashIntelReadStatus (UWORD32 Address)
//
//
// PARAMETERS : Address, Base Address of the flash package
//
// RETURN VALUE: UWORD16 contains the status of the flash package
//
//
// LIMITATIONS : Setup the MIF block before access to flash
//---------------------------------------------------------------------
UWORD16 FLASH_FlashIntelReadStatus (UWORD32 Address)
{
UWORD16 Status;
// Read the value of the status register
Status=ReadFlashRegister(Address,FLASH_READSTATUSDATA ,Address);
return Status;
}
void FLASH_FlashIntelClearStatus (UWORD32 Address)
{
// Clear status register
WriteFlash(Address,FLASH_CLEARSTATUS);
}
//---------------------------------------------------------------------
// NAME : FLASH_FlashIntelPairReadId
//
// DESCRIPTION : Get the Manufacturer id or the device id
//
// SYNOPSYS : UWORD32 FLASH_FlashIntelPairReadId(UWORD32 Address, BOOL IdRequest)
//
//
// PARAMETERS : Address, Base Address of the flash package
// IdRequest MANUFACTERER_ID_REQ or DEV16MBITBOTTOM_ID_REQ
//
// RETURN VALUE: UWORD32 the half MSB contains the status of the MSB flash package
// the half LSB contains the status of the LSB flash package
//
// LIMITATIONS : Setup the MIF block before access to flash
//---------------------------------------------------------------------
UWORD32 FLASH_FlashIntelPairReadId(UWORD32 Address, BOOL IdRequest)
{
UWORD32 Id;
UWORD32 Address1;
/* Undefined address should be within the device */
Address1 = FPAIR_UNDEFINEDADDRESS1 | Address;
if (IdRequest==MANUFACTERER_ID_REQ)
{
// Read the value of the manufacturer id
Id=ReadFlashPairRegister(Address1,FPAIR_READIDCODES,Address1);
}
else
{
// Read the value of the device id
Id=ReadFlashPairRegister(Address1,FPAIR_READIDCODES,(Address1+4));
}
/* Read Array command to terminate operation */
REG32(Address1) = FPAIR_READARRAYDATA;
return Id;
}
//---------------------------------------------------------------------
// NAME : FLASH_FlashIntelReadId
//
// DESCRIPTION : Get the Manufacturer id or the device id
//
// SYNOPSYS : UWORD16 FLASH_FlashIntelPairReadId(UWORD32 Address, BOOL IdRequest)
//
//
// PARAMETERS : Address, Base Address of the flash package
// IdRequest MANUFACTERER_ID_REQ or DEV16MBITBOTTOM_ID_REQ
//
// RETURN VALUE: UWORD16 contains the status of the flash package
//
// LIMITATIONS : Setup the MIF block before access to flash
//---------------------------------------------------------------------
UWORD16 FLASH_FlashIntelReadId(UWORD32 Address, BOOL IdRequest)
{
UWORD16 Id;
UWORD32 Address1;
/* Undefined address should be within the device */
Address1 = FPAIR_UNDEFINEDADDRESS1 | Address;
if (IdRequest==MANUFACTERER_ID_REQ)
{
// Read the value of the manufacturer id
Id=ReadFlashRegister(Address1,(UWORD16)FPAIR_READIDCODES,Address1);
}
else
{
// Read the value of the device id
Id=ReadFlashRegister(Address1,(UWORD16)FPAIR_READIDCODES,(Address1+2));
}
return Id;
}
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