tpu.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//=====================================================================  
//       TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION             
// Property of Texas Instruments -- For Unrestricted Internal Use Only   
// Unauthorized reproduction and/or distribution is strictly prohibited  
// This product is protected under copyright law and trade secret law as 
// an unpublished work.Created 2001,(C) Copyright 2001 Texas Instruments.
// All rights reserved.                                                  
//=====================================================================  

#include "tpu.h"

#include "global_types.h"
#include "mapping.h"
#include "result.h"


/* Definition of functions */

//---------------------------------------------------------------------------------
//  TPU_LoadScenario : Write a null-terminated scenario into TPU memory 
//---------------------------------------------------------------------------------
void TPU_LoadScenario(const UWORD16 code[])
{
   UWORD16 *addr;
   UWORD16 num;
   
   num = 0;
   addr = (UWORD16 *) TPU_RAM_BASE_ADDR_ARM;

   // Write TPU instructions into TPU RAM until SLEEP instruction is read  
   do
   {
      *addr++ = code[num];       
   }
   while (code[num++]);    

}

//---------------------------------------------------------------------------------
//  TPU_LoadScenarios : Write a null-terminated scenario into TPU memory 
//---------------------------------------------------------------------------------
void TPU_LoadScenarios(const UWORD16 code1[], const UWORD16 code2[])
{
   UWORD16 *addr_first_p, *addr_second_p;
   UWORD16 num;
   
   num = 0;	/* Reset loop counter */

   addr_first_p  = (UWORD16 *) TPU_RAM_BASE_ADDR_ARM;			/* Pointer on first  page */
   addr_second_p = (UWORD16 *) (TPU_RAM_BASE_ADDR_ARM + MAP_TPU_PAGE);	/* Pointer on second page */

   // Write TPU instructions into first TPU RAM page   
   do
   {
      *addr_first_p++ = code1[num];       
   }
   while (code1[num++]);    

   num = 0;	/* Reset loop counter */

   // Write TPU instructions into second TPU RAM page   
   do
   {
      *addr_second_p++ = code2[num];       
   }
   while (code2[num++]);    

}


//---------------------------------------------------------------------------------
//  TPU_PatchWr : Change a value in TPU RAM 
//---------------------------------------------------------------------------------
void TPU_PatchWr(UWORD16 offset, UWORD16 value)
{
   UWORD16 *addr;

   addr = (UWORD16 *) (TPU_RAM_BASE_ADDR_ARM + 2 * offset);
   *addr = value;
   
}

//---------------------------------------------------------------------------------
//  TPU_PatchRd : Read a value in TPU RAM 
//---------------------------------------------------------------------------------
UWORD16 TPU_PatchRd(UWORD16 offset)
{
   UWORD16 *addr;

   addr = (UWORD16 *) (TPU_RAM_BASE_ADDR_ARM + 2 * offset);
   return (*addr);   
}


//---------------------------------------------------------------------------------
//  TPU_Reset : Reset the TPU
//---------------------------------------------------------------------------------
void TPU_Reset(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TPU_CTRL_RST_TPU_MASK):
       (TPU_CTRL_REG &= ~TPU_CTRL_RST_TPU_MASK);
}
 


//---------------------------------------------------------------------------------
//  TPU_ResetTsp : Reset the TSP module
//---------------------------------------------------------------------------------
void TPU_ResetTsp(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TSP_CTRL_RST_TSP_MASK):
       (TPU_CTRL_REG &= ~TSP_CTRL_RST_TSP_MASK);
}


//---------------------------------------------------------------------------------
//  TPU_ClkEnable : Enable the TPU clock
//---------------------------------------------------------------------------------
void TPU_ClkEnable(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TPU_CTRL_CLK_EN_MASK):
       (TPU_CTRL_REG &= ~TPU_CTRL_CLK_EN_MASK);
}

//---------------------------------------------------------------------------------
//  TPU_Enable : Enable the execution of a new scenario
//---------------------------------------------------------------------------------
void TPU_Enable(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TPU_CTRL_TPU_ENBL_MASK):
       (TPU_CTRL_REG &= ~TPU_CTRL_TPU_ENBL_MASK);
}


//---------------------------------------------------------------------------------
//  TPU_CtrlRamTest : Enable TPU RAM reading
//---------------------------------------------------------------------------------
void TPU_CtrlRamTest(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TPU_CTRL_RAMTEST_MASK):
       (TPU_CTRL_REG &= ~TPU_CTRL_RAMTEST_MASK);
}


//---------------------------------------------------------------------------------
//  TPU_FullWrite : Enable Full Write mode
//---------------------------------------------------------------------------------
void TPU_FullWrite(UWORD8 on)
{
   (on == FUNCTION_ON) ?
       (TPU_CTRL_REG |=  TPU_CTRL_FULL_WR_MASK):
       (TPU_CTRL_REG &= ~TPU_CTRL_FULL_WR_MASK);
}

//---------------------------------------------------------------------------------
//  TPU_TestRegisters : Access test to the registers of the TPU and TSP modules
//---------------------------------------------------------------------------------
UWORD16 TPU_TestRegisters(void)
{
 UWORD16 val; 
 UWORD16 err=RES_OK;

  /* Get init. value of offset register */
  val = (TPU_OFFSET_REG & TPU_OFFSET_MASK);
  if (val != TPU_OFFSET_INIT_VALUE)
  {
     RES_Set(0x02);
     RES_Set(val);
     err = RES_BAD;
  }
  
  /* Get init. value of synchro register */
  val = (TPU_SYNCHRO_REG & TPU_SYNCHRO_MASK);
  if (val != TPU_SYNCHRO_INIT_VALUE)
  {
     RES_Set(0x03);
     RES_Set(val);
     err = RES_BAD;
  }
   
  /* Get init. value of control register */
  val = (TPU_CTRL_REG & TPU_CTRL_MASK);
  if (val != TPU_CTRL_INIT_VALUE)
  {
      RES_Set(0x04);
      RES_Set(val);
      err = RES_BAD;
  }
  
  /* Get init. value of interrupt control register */
  val = (TPU_INT_CTRL_REG & TPU_INT_CTRL_MASK);
  if (val != TPU_INT_CTRL_INIT_VALUE)
  {
     RES_Set(0x05);
     RES_Set(val);
     err = RES_BAD;
  }
 
  /* Get init. value of interrupt status register */
  val = (TPU_INT_STAT_REG & TPU_INT_STAT_MASK);
  if (val != TPU_INT_STAT_INIT_VALUE)
  {
     RES_Set(0x06);
     RES_Set(val);
     err = RES_BAD;
  }	
 
  /* Get init. value of receive LSB register */
  if ( TSP_RX_LSB != TSP_RX_INIT_VALUE )
  {
      RES_Set(0x07);
      RES_Set(val);
      err = RES_BAD;
  }	
 
  /* Get init. value of receive MSB register */
  if ( TSP_RX_MSB != TSP_RX_INIT_VALUE )
  {
     RES_Set(0x08);
     RES_Set(val);
     err = RES_BAD;
  }	
   
  /* Get init. value of transmit LSB register */
  if ( TSP_TX_LSB != TSP_RX_INIT_VALUE )
  {
      RES_Set(0x09);
      RES_Set(val);
      err = RES_BAD;
  }	
 
  /* Get init. value of transmit MSB register */
  if ( TSP_TX_MSB != 0x0000 )
  {
     RES_Set(0x0a);
     RES_Set(val);
     err = RES_BAD;
  }	
 
  return err;
}

//----------------------------------------------------------
//   TPU_ReadPage : Return visible page by TPU
//----------------------------------------------------------
boolean_t TPU_ReadPage(void)
{  
  return ((TPU_CTRL_REG&TPU_CTRL_TPU_PAGE_MASK)>>1);
}	

//----------------------------------------------------------
//   TPU_ReadCtrlReg 
//----------------------------------------------------------
UWORD16 TPU_ReadCtrlReg(void)
{  
  return ( TPU_CTRL_REG );
}	

//----------------------------------------------------------
//   TPU_SetCtrlReg 
//----------------------------------------------------------
void TPU_SetCtrlReg(UWORD16 value)
{  
  TPU_CTRL_REG |= value;
}	

//----------------------------------------------------------
//   TPU_EnableIt 
//----------------------------------------------------------
void TPU_EnableIt(UWORD8 type)
{  
   switch (type)
     {
       case 1 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITF_M_MASK);
		break;

       case 2 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITP_M_MASK);
		break;

       case 3 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITD_M_MASK | TPU_INT_CTRL_ITD_F_MASK);
		TPU_CTRL_REG     |=  (TPU_CTRL_DSP_ENBL_MASK);
		break;

       case 4 :
       		TPU_INT_CTRL_REG |=  (TPU_INT_CTRL_ITD_M_MASK | TPU_INT_CTRL_ITD_F_MASK);
		TPU_CTRL_REG     &= ~(TPU_CTRL_DSP_ENBL_MASK);       		
		break;

       case 5 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITF_M_MASK | TPU_INT_CTRL_ITP_M_MASK |
				      TPU_INT_CTRL_ITD_M_MASK | TPU_INT_CTRL_ITD_F_MASK  );
		TPU_CTRL_REG     |=  (TPU_CTRL_DSP_ENBL_MASK);
		break;

       case 6 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITF_M_MASK | TPU_INT_CTRL_ITP_M_MASK);
       		TPU_INT_CTRL_REG |=  (TPU_INT_CTRL_ITD_M_MASK | TPU_INT_CTRL_ITD_F_MASK);
		TPU_CTRL_REG     &= ~(TPU_CTRL_DSP_ENBL_MASK);       		
		break;
		
    }		
}	

//----------------------------------------------------------
//   TPU_DisableIt 
//----------------------------------------------------------
void TPU_DisableIt(UWORD8 type)
{  
   switch (type)
     {
       case 1 :
       		TPU_INT_CTRL_REG |= (TPU_INT_CTRL_ITF_M_MASK);
		break;

       case 2 :
       		TPU_INT_CTRL_REG |= (TPU_INT_CTRL_ITP_M_MASK);
		break;

       case 3 :
       		TPU_INT_CTRL_REG |=  (TPU_INT_CTRL_ITD_M_MASK);
		TPU_CTRL_REG     &= ~(TPU_CTRL_DSP_ENBL_MASK);
		break;

       case 4 :
       		TPU_INT_CTRL_REG &= ~(TPU_INT_CTRL_ITD_F_MASK);
		break;

       case 7 :
       		TPU_INT_CTRL_REG |=  (TPU_INT_CTRL_ITF_M_MASK | TPU_INT_CTRL_ITP_M_MASK |
				      TPU_INT_CTRL_ITD_M_MASK);
       		TPU_INT_CTRL_REG &=  ~(TPU_INT_CTRL_ITD_F_MASK);
		TPU_CTRL_REG     &= ~(TPU_CTRL_DSP_ENBL_MASK);
		break;
    }		
}