intvecs.asm.aptix

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

;******************************************************************************
;            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
;                                                                             
;   Property of Texas Instruments 
;   For  Unrestricted  Internal  Use  Only
;   Unauthorized reproduction and/or distribution is strictly prohibited.  
;   This product is protected under copyright law and trade secret law 
;   as an unpublished work.	
; 
;   Created 1999, (C) Copyright 1999 Texas Instruments.  All rights reserved.
;
; 
;******************************************************************************* 

	.state32
        .global _reset
        .global _c_int00
        .global _EX_AbortD
        .global _EX_Irq
        .global _EX_Fiq
        .global INT_Swi

	.global $INT_SetSupervisor
	.global $INT_SetUser        
        .global $INT_EnableIRQ
        .global $INT_EnableFIQ
	.global $INT_SetIRQBit
        .global $INT_ClearIRQBit
	.global $INT_SetFIQBit
        .global $INT_ClearFIQBit
	.global $INT_Set_SVC_Stack
	.global $INT_Set_AbortD_Stack

        .sect ".intvecs"

_reset	LDR	pc, initBasicCall       ;  RESET INTERRUPT
undef:	B       undef           	;  UNDEFINED INSTRUCTION INTERRUPT
        LDR     pc, INT_SwiCall         ;  SOFTWARE INTERRUPT
abort1: B       abort1                  ;  ABORT (PREFETCH) INTERRUPT
	LDR     pc, _EX_AbortDCall      ;  ABORT (DATA) INTERRUPT
reserv: B	reserv                  ;  RESERVED
        LDR	pc, _EX_IrqCall         ;  IRQ INTERRUPT
        LDR	pc, _EX_FiqCall         ;  FIQ INTERRUPT

IRQ_MASK        .equ     0x80           ; IRQ mask value
FIQ_MASK        .equ     0x40           ; FIQ mask value
MODE_MASK       .equ     0x1F           ; Processor Mode Mask

FIQ_MODE        .equ     0x11           ; Fast Interrupt Mode (FIQ)
IRQ_MODE        .equ     0x12           ; Interrupt Mode (IRQ)
SUP_MODE        .equ     0x13           ; Supervisor Mode
USR_MODE        .equ     0x10           ; User Mode
ABORT_MODE      .equ     0x17           ; Abort Mode
SYS_MODE        .equ     0x1F           ; System mode

CLEAR_BIT       .equ     0x00           ; Clear Bit
SET_BIT         .equ     0x01           ; Set Bit	

initBasicCall	.word initBasic
	
INT_SwiCall	.word INT_Swi
	
_EX_AbortDCall	.word _EX_AbortD
	
_EX_IrqCall	.word _EX_Irq

_EX_FiqCall	.word _EX_Fiq

       .sect ".boot"

; Basic Initializations

initBasic:	
        ;; -------Flush Instruction cache-------
        ;; --------------------------------------
	MOV	r1,#0
	MCR	p15, #0, r1, c7, c5  ; Flush Instruction Cache

        ;; -------Enable Instruction cache-------
        ;; --------------------------------------
        MRC	p15, #0, R1, C1, C0
        ORR	R1, R1, #0x1000
        MCR	P15, #0, R1, C1, C0
        ;; --------------------------------------

;
; Initialize Emif Slow Chip-Select Config register
; For CS3
;
	LDR	r0, addrSlowConfRegCS3				
	LDR	r1, valueSlowConfRegCS3_16bits                  
	STR	r1, [r0]					

; Set the SMIF CS1 clock divider by 2 + 16 bits
	LDR     r1,MIF_DIV_BY2_MASK ; must clear this bit to allow divide by 2
	LDR     r3,BusWidthMask     ; must clear this bit to allow 16 bits access
	ORR     r3, r3, r1
        LDR     R0,MIF_CS1_reg
        LDR     R2,[R0]
        BIC     R2,R2,R3
        STR     R2,[R0]

; Set the SMIF CS2 clock divider by 2
        LDR     R0,MIF_CS2_reg
        LDR     R2,[R0]
        BIC     R2,R2,R1
        STR     R2,[R0]

; SDRAM initialisation 
      	LDR	R0, AddrEmifFast
	LDR	R1, ValueEmifFast
	STR	R1, [R0]		

	LDR	R0, AddrEmifFastMRS
	LDR	R1, ValueEmifFastMRS
	STR	R1, [R0]		
                
; Set the synchronous scalable mode
        LDR     r0,ARM_SYSST_reg
        LDR     R1,ARM_SYSST_val
        STR     R1,[R0]


; Set Clock divider tree and turn off DSP clock
        LDR     R0,ARM_CKCTL_reg
        LDR     R1,ARM_CKCTL_val
        STR     R1,[R0]
        
; Set the dpll ratios
;        LDR	R0, AddrDpll
;        LDR	R1, ValueDpll
;        STRH	R1, [R0]	
;	MOV     r4, #1	

; Wait for DPLL lock
;wait_dpll_lock:
;	LDR     r2, [r0]
;	TST     r2, r4
;	BEQ     wait_dpll_lock

; Sets up stack for various privileged modes
stack_setup:
	LDR     r0, privilege_stack_base
	MOV     r1, #0x50
;
; SWI handler needs to be called in thumb mode, so that the SWI function
; can be directly called from C code. We switch to thumb mode
;
	ADR	r2, to_thumb + 1
	BX	r2
	.state16
to_thumb:
;
; Sets up SVC stack
;
	SWI     #0xF5
;
; Sets up DATA ABORT stack
;
; r1 contains size of stack (in words = 0x50)
	MOV     r1, #0x50
	LSL	r2, r1, #2
; r0 contains stack base address (= previous base address + size*4)
	ADD	r0, r2
	SWI	#0xF4 
;
; Sets up FIQ stack and enables FIQ
;
	MOV     r1, #0x50
	LSL	r2, r1, #2
	ADD	r0, r2
	SWI     #0xFC
;
; Sets up IRQ stack and enables IRQ
;
	MOV     r1, #0x50
	LSL	r2, r1, #2
	ADD	r0, r2
	SWI     #0xFD
;
; Back to ARM mode
        ADR r0, to_arm_code         ; Switch to ARM mode
        BX  r0

	.state32
to_arm_code:

; Enable ARM PERCK
        LDR     R0, ARM_IDLECT2_reg
        LDR     R1, [R0]
        ORR     R1, R1, #0x4
        STR     R1, [R0]

; Release ARM peripheral reset
        LDR     R0, ARM_RSTCT2_reg
        LDR     R1, [R0]
        ORR     R1, R1, #0x1
        STR     R1, [R0]

; Enable system clock out of the ULPD (for GPIOS)
        LDR	r0, ulpd_cam_clk_ctrl_addr
	LDRH    r1, [r0]
	ORR     r1, r1, #0x4
	STRH    r1, [r0]
		
; Disable pulldown on NFRDY
	LDR	r0, conf_pull_dwn_ctrl_4_addr
	LDR	r1, [r0]
	ORR	r1, r1, #0x8
	STR	r1, [r0] 

; Initialize ARM925T internal registers.
	MOV	R0, #0
	MOV	R1, #0
	MOV	R2, #0
	MOV	R3, #0
	MOV	R4, #0
	MOV	R5, #0
	MOV	R6, #0
	MOV	R7, #0
	MOV	R8, #0
	MOV	R9, #0
	MOV	R10, #0
	MOV	R11, #0
	MOV	R12, #0
	
	LDR	r0, prog_entry  
	MOV	pc, r0   ; RESET INTERRUPT

;; ===========================================================================================
prog_entry			.word	_c_int00

;
; Privilege stacks are put in SDRAM
;
privilege_stack_base            .word   0x107FC000

addrSlowConfRegCS0	        .word   0xFFFECC10
addrSlowConfRegCS3	        .word   0xFFFECC1C
BusWidthMask    	        .word   0x00100000
                                                         ;    0000_0000_00       0                           1
valueSlowConfRegCS0_32bits	  .word   0x00304069 ; [b XXXX_XXXX_XX(1)(1)_X(000)_(0100)_(0000)_(0110)_X(0)(01)] 
                                                     ;                 FL BW RDMODE  PGWST  WRWST  RDWST  RT  FCLKDIV
valueSlowConfRegCS0_16bits	  .word   0x00204069 ; [b XXXX_XXXX_XX(1)(0)_X(000)_(0100)_(0000)_(0110)_X(0)(01)] 
                                                     ;                 FL BW RDMODE  PGWST  WRWST  RDWST  RT  FCLKDIV
valueSlowConfRegCS3_16bits	  .word   0x00001188 ; [b XXXX_XXXX_XX(0)(0)_X(000)_(0001)_(0001)_(1000)_X(0)(00)] 
;      for  96MHz                                    ;                 FL BW RDMODE  PGWST  WRWST  RDWST  RT  FCLKDIV
;      for a flash to 70ns response time with a marge of 20ns: at 10.4 ns (96MHz)  -> 90ns = 8.65 ~ 9 periods so 8 RDWST
 
AddrEmifFast      	        .word   0xFFFECC20
;ValueEmifFast               	.word   0x0C020BF4    ; SDRAM 256 Mbit
;ValueEmifFast                 	.word   0x0C020BB4    ; SDRAM 128 Mbit
;ValueEmifFast                 	.word   0x0D039174    ;;with auto refresh counter = 913 =0x0391 
                                                      ;; 912.5 = 64 * 84 /4.096 - 400(for 84MHZ on TC )
ValueEmifFast                 	.word   0x0D000C74    ;MFP was 0x0D044C74 
;ValueEmifFast                 	.word   0x0D044C74    ;;with auto refresh counter = 1100 =0x044C 
;                                                     ;; 1100 = 64 * 96 /4.096 - 400 (for 96MHZ on TC )
;ValueEmifFast                 	.word   0x0D04A974    ;;with auto refresh counter = 1193 =0x04A9 
;                                                     ;; 1193 = 64 * 102 /4.096 - 400 (for 102MHZ on TC )
;ValueEmifFast                 	.word   0x0C020B74    ; SDRAM 64 Mbit
;ValueEmifFast                 	.word   0x0C000474
        ;;               MIF_SELF_REFRESH_DISABLE
        ;;               0,                      
        ;;               MIF_AUTO_REFRESH_ENABLE,
        ;;               7,                         SDRAM type: 64 Meg
        ;;               523,                      Counter
        ;;               MIF_SDRAM_FREQ_0,
        ;;               MIF_POWER_DOWN_ENABLE,  
        ;;               MIF_SDRAM_CLOCK_ENABLE
        ;;

AddrEmifFastMRS                 .word   0xFFFECC24
;ValueEmifFastMRS                .word   0x00000037
ValueEmifFastMRS                .word   0x00000027
        ;;               burst full-page lenght
	;;               cas latency = 3
	         
ARM_SYSST_reg                   .word   0xFFFECE18
; bit 12 allows to select the synchronous scalable mode
ARM_SYSST_val                   .word   0x00001000
      
MIF_CS0_reg                     .word   0xFFFECC10