📄 serial_dolo.c
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UMOD_InitDivLatch(DLL_Low, DLL_High, UartSerialType);
}
else
{
UARTIRDA_OSC_REG=1;
Rate_value = (UWORD16) BaudRate;
if (uart48Mhz)
Rate_value = Rate_value *4;
// Set DLL and DLH
DLL_High = (UWORD8) Rate_value >> 8;
DLL_Low = (UWORD8) Rate_value & 0xFF;
UIRD_InitDivLatch(DLL_Low, DLL_High);
}
}
}
}
/*
------------------------------------------------------------------------
NAME : SERIAL_configure
DESCRIPTION : Initialize and configure the specified UART
to assume the exchanges with the PC terminal.
PARAMETERS : Baude Rate, frame format and Uart Name
RETURN VALUE : None
LIMITATIONS : None
------------------------------------------------------------------------
*/
void SERIAL_configure(const SERIAL_Uart_t UartType,
const UARTMOD_BaudRate_t BaudRate,
const UARTMOD_CharLength_t CharLength,
const UARTMOD_NbStop_t NbStop,
const UARTMOD_ParityEnable_t ParityEnable,
const UARTMOD_ParityType_t ParityType)
{
UWORD8 DLL_High ;
UWORD8 DLL_Low ;
UWORD16 Rate_value ;
switch (UartType)
{
case SERIAL_UART_BLUETOOTH :
if (uart48Mhz)
{
MUX_uart1_clk48();
// wait till request is take into account by ULPD
while ((STATUS_REQ_REG_REG & (1<< UART1_DPLL_REQ_POS))== 0) ;
}
// Configure the UART 1 interface at Dolomites Top Level
DCONF_BLUETOOTH_UART_IF(DCONF_MODE_0);
break;
case SERIAL_UART_EVALUATION :
break;
case SERIAL_UART_MODEM :
if (uart48Mhz)
{
MUX_uart2_clk48();
// wait till request is take into account by ULPD
while ((STATUS_REQ_REG_REG & (1<< UART2_DPLL_REQ_POS))== 0);
}
// Configure the UART 2 interface at Dolomites Top Level
DCONF_MMC_IF(DCONF_MODE_3);
break;
case SERIAL_UART_IRDA :
if (uart48Mhz)
{
MUX_uart3_clk48();
// wait till request is take into account by ULPD
while ((STATUS_REQ_REG_REG & (1<< UART3_DPLL_REQ_POS))== 0) ;
}
// Configure the UART 4 interface at Dolomites Top Level
DCONF_IRDA_UART_IN_MODEM_MODE();
break;
}
UartSerialType = UartType;
if (UartSerialType != SERIAL_UART_IRDA)
{
UMOD_InitMdr1(UARTMOD_RESET_DEFAULT_SELECT,UartType);
// ---------------------------------------------------
// ----- INIT UART -----------------------------------
// ---------------------------------------------------
// --- Sequence for change baud rate ---
// set regiter LCR=0xBF for accsess to EFR register
UMOD_InitLcr(CharLength,
NbStop,
ParityEnable,
ParityType,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_GRANT_DIVISOR_LATCH_ACCESS,
UartType);
// IER[7:4] can only modified and enabled if EFR[4] is set
UMOD_InitEfr(UARTMOD_RX_NO_FLOW,
UARTMOD_TX_NO_FLOW,
UARTMOD_ENABLE_WRITE_IER,
UARTMOD_DISABLE_SPECIAL_CHAR_DETECT,
UARTMOD_DISABLE_AUTO_RTS,
UARTMOD_DISABLE_AUTO_CTS,
UartType);
// Set no Interrupt config and set disable sleep mode for config divisor latches
UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
// write in fcr should be done before setting DLH and DLL register
// Used for clear FIFO
//UARTMOD_InitFCR(UARTMOD_ENABLE_FIFOS,
UMOD_InitFcr(UARTMOD_DISABLE_FIFOS,
UARTMOD_CLEAR_RX_FIFO,
UARTMOD_CLEAR_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_32_SPACES_FIFO_TRIGGER,
UARTMOD_RX_16_CHARS_FIFO_TRIGGER,
UartType);
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
// DMA mode 0 for used mask dma_reg, trig. TX FIFO , trig.RX FIFO
//UARTMOD_InitFCR(UARTMOD_DISABLE_FIFOS,
UMOD_InitFcr(UARTMOD_ENABLE_FIFOS,
UARTMOD_NOCHANGE_RX_FIFO,
UARTMOD_NOCHANGE_TX_FIFO,
UARTMOD_DMA_MODE_0,
UARTMOD_TX_32_SPACES_FIFO_TRIGGER,
UARTMOD_RX_16_CHARS_FIFO_TRIGGER,
UartType);
//Set the UART Modem latch in 6.5 divisor
if (UartType != UART_EVALUATION)
{
UARTMOD_OSC_REG(UartType)=1;
Rate_value = (UWORD16) BaudRate;
}
else
Rate_value = (UWORD16) (BaudRate*6.5);
if (uart48Mhz)
Rate_value = Rate_value *4;
// Set DLL and DLH
DLL_High = (UWORD8) Rate_value >> 8;
DLL_Low = (UWORD8) Rate_value & 0xFF;
UMOD_InitDivLatch(DLL_Low, DLL_High, UartType);
// --- Config trame ---
UMOD_InitLcr(CharLength,
NbStop,
ParityEnable,
ParityType,
UARTMOD_NO_BREAK_CONDITION,
UARTMOD_NO_DIVISOR_LATCH_ACCESS,
UartType);
UMOD_ReadIir(UartType);
// mode select :start up after config registers DLL,DLH,LCR ..
UMOD_InitMdr1(UARTMOD_UART_SELECT, UartType);
// --- init interrupts ---
// Set no Interrupt config and set disable sleep mode for config divisor latches
UMOD_InitIer(UARTMOD_MASK_RHR_IT,
UARTMOD_MASK_THR_IT,
UARTMOD_MASK_LINE_STS_IT,
UARTMOD_MASK_MODEM_STS_IT,
UARTMOD_MASK_SLEEP_MODE,
UARTMOD_MASK_XOFF_IT,
UARTMOD_MASK_RTS_IT,
UARTMOD_MASK_CTS_IT,
UartType);
// read line status register
UMOD_ReadLsr(UartType);
}
else
{
UIRD_InitMdr1(UARTIRDA_UART_SELECT,
UARTIRDA_DISABLE_SLEEP,
UARTIRDA_ASAP_START,
UARTIRDA_FRAME_LENGTH_METHOD);
// ---------------------------------------------------
// ----- INIT UART -----------------------------------
// ---------------------------------------------------
// --- Sequence for change baud rate ---
// set regiter LCR=0xBF for accsess to EFR register
UIRD_InitLcr(CharLength,
NbStop,
ParityEnable,
ParityType,
UARTIRDA_NO_BREAK_CONDITION,
UARTIRDA_GRANT_DIVISOR_LATCH_ACCESS);
// IER[7:4] can only modified and enabled if EFR[4] is set
UIRD_InitEfr(UARTIRDA_RX_NO_FLOW,
UARTIRDA_TX_NO_FLOW,
UARTIRDA_ENABLE_WRITE_IER,
UARTIRDA_DISABLE_SPECIAL_CHAR_DETECT,
UARTIRDA_DISABLE_AUTO_RTS,
UARTIRDA_DISABLE_AUTO_CTS);
// Set no Interrupt config and set disable sleep mode for config divisor latches
UIRD_InitIer(UARTIRDA_MASK_RHR_IT,
UARTIRDA_MASK_THR_IT,
UARTIRDA_MASK_LINE_STS_IT,
UARTIRDA_MASK_MODEM_STS_IT,
UARTIRDA_MASK_SLEEP_MODE,
UARTIRDA_MASK_XOFF_IT,
UARTIRDA_MASK_RTS_IT,
UARTIRDA_MASK_CTS_IT);
// write in fcr should be done before setting DLH and DLL register
// Used for clear FIFO
//UARTIRDA_InitFCR(UARTIRDA_ENABLE_FIFOS,
UIRD_InitFcr(UARTIRDA_DISABLE_FIFOS,
UARTIRDA_CLEAR_RX_FIFO,
UARTIRDA_CLEAR_TX_FIFO,
UARTIRDA_DMA_MODE_0,
UARTIRDA_TX_32_SPACES_FIFO_TRIGGER,
UARTIRDA_RX_16_CHARS_FIFO_TRIGGER);
//--- Program FIFO and DMA mode ---
// FIFO BYPASS in TX and Rx =0, clear FIFO Rx =0 don't care, Clear FIFO tx= 0 don't care,
// DMA mode 0 for used mask dma_reg, trig. TX FIFO , trig.RX FIFO
//UARTIRDA_InitFCR(UARTIRDA_DISABLE_FIFOS,
UIRD_InitFcr(UARTIRDA_ENABLE_FIFOS,
UARTIRDA_NOCHANGE_RX_FIFO,
UARTIRDA_NOCHANGE_TX_FIFO,
UARTIRDA_DMA_MODE_0,
UARTIRDA_TX_32_SPACES_FIFO_TRIGGER,
UARTIRDA_RX_16_CHARS_FIFO_TRIGGER);
UARTIRDA_OSC_REG=1;
Rate_value = (UWORD16) BaudRate;
if (uart48Mhz)
Rate_value = Rate_value *4;
// Set DLL and DLH
DLL_High = (UWORD8) Rate_value >> 8;
DLL_Low = (UWORD8) Rate_value & 0xFF;
UIRD_InitDivLatch(DLL_Low, DLL_High);
// --- Config trame ---
UIRD_InitLcr(CharLength,
NbStop,
ParityEnable,
ParityType,
UARTIRDA_NO_BREAK_CONDITION,
UARTIRDA_DENY_DIVISOR_LATCH_ACCESS);
UIRD_ReadIir();
// mode select :start up after config registers DLL,DLH,LCR ..
UIRD_InitMdr1(UARTIRDA_UART_SELECT,
UARTIRDA_DISABLE_SLEEP,
UARTIRDA_ASAP_START,
UARTIRDA_FRAME_LENGTH_METHOD);
// --- init interrupts ---
// Set no Interrupt config and set disable sleep mode for config divisor latches
UIRD_InitIer(UARTIRDA_MASK_RHR_IT,
UARTIRDA_MASK_THR_IT,
UARTIRDA_MASK_LINE_STS_IT,
UARTIRDA_MASK_MODEM_STS_IT,
UARTIRDA_MASK_SLEEP_MODE,
UARTIRDA_MASK_XOFF_IT,
UARTIRDA_MASK_RTS_IT,
UARTIRDA_MASK_CTS_IT);
// read line status register
UIRD_Readlsr();
}
}
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