📄 rheabridge.c
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/*
===============================================================================
// TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
//
// Property of Texas Instruments
// For Unrestricted Internal Use Only
// Unauthorized reproduction and/or distribution is strictly prohibited.
// This product is protected under copyright law and trade secret law
// as an unpublished work.
// Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
//
// Filename : rheabridge.c
//
// Description : Body file for the rhea bridge module
//
// Project : ARM925ST
//
// Author : Francis Huguenin fhugueni@tif.ti.com
//
===============================================================================
*/
#include "rheabridge.h"
#include "mem.h"
/* Base Address of Rhea Bridge configuration register only accessible in Supervisor Mode Read/Write*/
#define RHEA_BRIDGE_SUPERVISOR_ADDR MEM_RHEA_BRIDGE_SUPERVISOR_ADDR
/* Base Address of Rhea Bridge configuration register User Mode Read Only */
#define RHEA_BRIDGE_USER_ADDR MEM_RHEA_BRIDGE_USER_ADDR
/*
----------------------------------------------------
DMA SOURCE ADDRESS REGISTER -
----------------------------------------------------
*/
#define DMA_SOURCE_ADDRESS_REG_RESET_VALUE 0x00000000
#define DMA_SRC_SDRAM_ADDR_MSK 0x03FFFFFF /* SDRAM port address Mask */
#define DMA_SRC_EMIF_ADDR_MSK 0x03FFFFFF /* EMIF port address Mask */
#define DMA_SRC_LOCAL_ADDR_MSK 0x7FFFFFFF /* LOCAL port Mask */
#define DMA_SRC_RHEA_ADDR_MSK 0x000007FF /* RHEA port address Mask */
#define DMA_SRC_RHEA_CS_MSK 0x000007FF /* SDRAM port chip select Mask */
#define DMA_SRC_SDRAM_ADDR_BITPOS 0 /* SDRAM port address Mask */
#define DMA_SRC_EMIF_ADDR_BITPOS 0 /* EMIF port address Mask */
#define DMA_SRC_LOCAL_ADDR_BITPOS 0 /* LOCAL port Mask */
#define DMA_SRC_RHEA_ADDR_BITPOS 0 /* RHEA port address Mask */
#define DMA_SRC_RHEA_CS_BITPOS 16 /* SDRAM port chip select Mask */
/*
--------------------------------------------------------------------------------
RHEA CONTROL 16 BITS REGISTER -
--------------------------------------------------------------------------------
*/
#define RHEA_CNTL_REG_OFFSET 0x00
#define RHEA_CNTL_REG_SUPERVISOR_ADDR ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_CNTL_REG_OFFSET )
#define RHEA_CNTL_REG_USER_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_CNTL_REG_OFFSET )
#define RHEA_CNTL_REG_RESET_VALUE 0xFFFF
#define RHEA_CNTL_REG_MASK 0x0FFFF
#define RHEA_CNTL_FACT_0_MASK 0x000F /* Mask of Division factor strobe 0 */
#define RHEA_CNTL_FACT_1_MASK 0x00F0 /* Mask of Division factor strobe 1 */
#define RHEA_CNTL_TIMEOUT_MASK 0xFF00 /* Mask of RHEA bus access timeout */
/* Bit position of Slow Strobe1 Access Factor */
#define RHEA_FACTOR_STROBE1_POS 4
/* Bit position of Rhea bus TimeOut */
#define RHEA_BUS_ACCESS_TIMEOUT_POS 8
/*
--------------------------------------------------------------------------------
RHEA BUS ALLOC 4 BITS REGISTER -
--------------------------------------------------------------------------------
*/
#define RHEA_BUS_ALLOC_REG_OFFSET 0x04
#define RHEA_BUS_ALLOC_REG_SUPERVISOR_ADDR ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )
#define RHEA_BUS_ALLOC_REG_USER_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_BUS_ALLOC_REG_OFFSET )
#define RHEA_BUS_ALLOC_REG_MASK 0x0F
#define RHEA_BUS_ALLOC_REG_RESET_VALUE 0x09
#define RHEA_PRIORITY_MASK 0x07 /* Mask of priority */
#define RHEA_PRIORITY_ENABLE_MASK 0x08 /* Mask of priority enable field */
#define RHEA_PRIORITY_ENABLE_POS 3 /* Start Bit position of priority enable */
/*
------------------------------------------------------------------------------------------
ARM RHEA CONTROL 4 BITS REGISTER -
------------------------------------------------------------------------------------------
*/
#define RHEA_ARM_CONTROL_REG_OFFSET 0x08
#define RHEA_ARM_CONTROL_REG_SUPERVISOR_ADDR ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )
#define RHEA_ARM_CONTROL_REG_USER_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_ARM_CONTROL_REG_OFFSET )
#define RHEA_ARM_CONTROL_REG_RESET_VALUE 0x00
#define RHEA_ARM_CONTROL_REG_MASK 0x03
/* Mask of write buffer toggle for strobe 0 */
#define RHEA_WRITE_BUFFER_TOGGLE_STROBE0_MASK 0x01
/* Mask of write buffer toggle for strobe 1 */
#define RHEA_WRITE_BUFFER_TOGGLE_STROBE1_MASK 0x02
/* Start Bit position OF write buffer toggle for strobe 1 */
#define RHEA_WRITE_BUFFER_TOGGLE_STROBE1_POS 1
/*
----------------------------------------------------------------------------------------------------
ENHANCED RHEA CONTROL 3 BITS REGISTER -
----------------------------------------------------------------------------------------------------
*/
#define RHEA_ENHANCED_CONTROL_REG_OFFSET 0x0C
#define RHEA_ENHANCED_CONTROL_REG_SUPERVISOR_ADDR ( RHEA_BRIDGE_SUPERVISOR_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )
#define RHEA_ENHANCED_CONTROL_REG_USER_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_ENHANCED_CONTROL_REG_OFFSET )
#define RHEA_ENHANCED_CONTROL_REG_RESET_VALUE 0xF
#define RHEA_ENHANCED_CONTROL_REG_MASK 0xF
#define RHEA_TIMEOUT_TOGGLE_MASK 0x01 /* Mask of Timeout Toggle */
#define RHEA_MASK_INTERRUPT_MASK 0x02 /* Mask of mask interrupt */
#define RHEA_HIGH_FREQ_TOGGLE_MASK 0x04 /* Mask of high frequency */
#define RHEA_MASK_ABORT_MASK 0x08 /* Mask of abort generation */
#define RHEA_MASK_INTERRUPT_POS 1 /* Start Bit position of mask interrupt */
#define RHEA_HIGH_FREQ_POS 2 /* Start Bit position of high frequency */
#define RHEA_MASK_ABORT_POS 3 /* */
/*
---------------------------------------------------------------------------------------------------
DEBUG ADDRESS REGISTER -
---------------------------------------------------------------------------------------------------
*/
#define RHEA_ADDRESS_DEBUG_REG_OFFSET 0x10
#define RHEA_ADDRESS_DEBUG_REG_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_ADDRESS_DEBUG_REG_OFFSET )
#define RHEA_ADDRESS_DEBUG_REG_RESET_VALUE 0xFFFF
#define RHEA_ADDRESS_DEBUG_MASK 0xFFFF /* Mask of address debug mask */
/*
----------------------------------------------------------------------------------------------------
DEBUG DATA LSB REGISTER -
----------------------------------------------------------------------------------------------------
*/
#define RHEA_DEBUG_DATA_LSB_REG_OFFSET 0x14
#define RHEA_DEBUG_DATA_LSB_REG_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_DEBUG_DATA_LSB_REG_OFFSET )
#define RHEA_DEBUG_DATA_LSB_RESET_VALUE 0xFFFF /* Reset value of debug data lsb */
#define RHEA_DEBUG_DATA_LSB_MASK 0xFFFF /* Mask of debug data lsb */
/*
----------------------------------------------------------------------------------------------------
DEBUG DATA MSB 16 BITS REGISTER -
----------------------------------------------------------------------------------------------------
*/
#define RHEA_DEBUG_DATA_MSB_REG_OFFSET 0x18
#define RHEA_DEBUG_DATA_MSB_REG_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_DEBUG_DATA_MSB_REG_OFFSET )
#define RHEA_DEBUG_DATA_MSB_RESET_VALUE 0xFFFF /* Mask of debug data msb */
#define RHEA_DEBUG_DATA_MSB_MASK 0xFFFF /* Mask of debug data msb */
/*
-----------------------------------------------------------------------------------------------------
DEBUG CONTROL SIGNAL 16 BITS REGISTER -
-----------------------------------------------------------------------------------------------------
*/
#define RHEA_DEBUG_CONTROL_SIGNAL_REG_OFFSET 0x1C
#define RHEA_DEBUG_CONTROL_SIGNAL_REG_ADDR ( RHEA_BRIDGE_USER_ADDR + RHEA_DEBUG_CONTROL_SIGNAL_REG_OFFSET )
#define RHEA_DEBUG_CONTROL_SIGNAL_REG_RESET_VALUE 0xFC
#define RHEA_ABORT_FLAG_MASK 0x01 /* Mask of abort notification */
#define RHEA_WR_SIZE_FLAG_MASK 0x02 /* Mask of mismatch write size */
#define RHEA_DBG_RNW_MASK 0x04 /* Mask of Read-Not write on rhea bus */
#define RHEA_DBG_NSPUV_MASK 0x08 /* Mask of not supervisor mode on rhea bus */
#define RHEA_DBG_MAS_MASK 0x30 /* Mask of memory access size on rhea bus */
#define RHEA_DBG_PERHMAS_MASK 0xC0 /* Mask of peripheral memory access size on rhea bus */
#define RHEA_DEBUG_CONTROL_SIGNAL_MASK 0xFF
#define RHEA_WR_SIZE_FLAG_POS 1 /* Start bit position of mismatch write size */
#define RHEA_DBG_RNW_POS 2 /* Start bit position of Read-Not write on rhea bus */
#define RHEA_DBG_NSPUV_POS 3 /* Start bit position of not supervisor mode on rhea bus */
#define RHEA_DBG_MAS_POS 4 /* Start bit position of memory access size on rhea bus */
#define RHEA_DBG_PERHMAS_POS 6 /* Start bit position of peripheral memory access size on rhea bus */
/*
--------------------------------------------------------------------------------
RHEA_GetStrobe0CsAddress -
--------------------------------------------------------------------------------
*/
/* unused function which takes long time to be initialize
UWORD32 RHEA_GetStrobe0CsAddress(RHEA_Strobe0ChipSelect_t ChipSelect)
{
static UWORD32 Strobe0CsAddress[MEM_RHEA_STROBE0_NUMBER_OF_CS]
= { MEM_RHEA_STROBE0_CS0_ADDR , MEM_RHEA_STROBE0_CS1_ADDR,
MEM_RHEA_STROBE0_CS2_ADDR , MEM_RHEA_STROBE0_CS3_ADDR,
MEM_RHEA_STROBE0_CS4_ADDR , MEM_RHEA_STROBE0_CS5_ADDR,
MEM_RHEA_STROBE0_CS6_ADDR , MEM_RHEA_STROBE0_CS7_ADDR,
MEM_RHEA_STROBE0_CS8_ADDR , MEM_RHEA_STROBE0_CS9_ADDR,
MEM_RHEA_STROBE0_CS10_ADDR, MEM_RHEA_STROBE0_CS11_ADDR,
MEM_RHEA_STROBE0_CS12_ADDR, MEM_RHEA_STROBE0_CS13_ADDR,
MEM_RHEA_STROBE0_CS14_ADDR, MEM_RHEA_STROBE0_CS15_ADDR,
MEM_RHEA_STROBE0_CS16_ADDR, MEM_RHEA_STROBE0_CS17_ADDR,
MEM_RHEA_STROBE0_CS18_ADDR, MEM_RHEA_STROBE0_CS19_ADDR,
MEM_RHEA_STROBE0_CS20_ADDR, MEM_RHEA_STROBE0_CS21_ADDR,
MEM_RHEA_STROBE0_CS22_ADDR, MEM_RHEA_STROBE0_CS23_ADDR,
MEM_RHEA_STROBE0_CS24_ADDR, MEM_RHEA_STROBE0_CS25_ADDR,
MEM_RHEA_STROBE0_CS26_ADDR, MEM_RHEA_STROBE0_CS27_ADDR
};
return Strobe0CsAddress[ChipSelect];
}
*/
/*
--------------------------------------------------------------------------------
RHEA_GetStrobe1CsAddress -
--------------------------------------------------------------------------------
*/
/* unused function which takes long time to be initialize
UWORD32 RHEA_GetStrobe1CsAddress(RHEA_Strobe1ChipSelect_t ChipSelect)
{
static UWORD32 Strobe1CsAddress[MEM_RHEA_STROBE1_NUMBER_OF_CS]
= { MEM_RHEA_STROBE1_CS0_ADDR , MEM_RHEA_STROBE1_CS1_ADDR,
MEM_RHEA_STROBE1_CS2_ADDR , MEM_RHEA_STROBE1_CS3_ADDR,
MEM_RHEA_STROBE1_CS4_ADDR , MEM_RHEA_STROBE1_CS5_ADDR,
MEM_RHEA_STROBE1_CS6_ADDR , MEM_RHEA_STROBE1_CS7_ADDR,
MEM_RHEA_STROBE1_CS8_ADDR , MEM_RHEA_STROBE1_CS9_ADDR,
MEM_RHEA_STROBE1_CS10_ADDR, MEM_RHEA_STROBE1_CS11_ADDR,
MEM_RHEA_STROBE1_CS12_ADDR, MEM_RHEA_STROBE1_CS13_ADDR,
MEM_RHEA_STROBE1_CS14_ADDR, MEM_RHEA_STROBE1_CS15_ADDR,
MEM_RHEA_STROBE1_CS16_ADDR, MEM_RHEA_STROBE1_CS17_ADDR,
MEM_RHEA_STROBE1_CS18_ADDR, MEM_RHEA_STROBE1_CS19_ADDR,
MEM_RHEA_STROBE1_CS20_ADDR, MEM_RHEA_STROBE1_CS21_ADDR,
MEM_RHEA_STROBE1_CS22_ADDR, MEM_RHEA_STROBE1_CS23_ADDR,
MEM_RHEA_STROBE1_CS24_ADDR, MEM_RHEA_STROBE1_CS25_ADDR,
MEM_RHEA_STROBE1_CS26_ADDR, MEM_RHEA_STROBE1_CS27_ADDR,
MEM_RHEA_STROBE1_CS28_ADDR, MEM_RHEA_STROBE1_CS29_ADDR,
MEM_RHEA_STROBE1_CS30_ADDR, MEM_RHEA_STROBE1_CS31_ADDR
};
return Strobe1CsAddress[ChipSelect];
}
*/
/*
----------------------------------------------------------------------------------------
RHEA_InitControlReg -
----------------------------------------------------------------------------------------
*/
void RHEA_InitCtrolReg(const RHEA_AccessFactorStrobe_t FactorStrobe0,
const RHEA_AccessFactorStrobe_t FactorStrobe1,
const UWORD8 TimeOutValue)
{
REG16(RHEA_CNTL_REG_SUPERVISOR_ADDR)
= ( FactorStrobe0
| FactorStrobe1 << RHEA_FACTOR_STROBE1_POS
| TimeOutValue << RHEA_BUS_ACCESS_TIMEOUT_POS );
}
/*
-------------------------------------------------------------------------
RHEA_SetTimeOut -
-------------------------------------------------------------------------
*/
void RHEA_SetTimeOut(const UWORD8 TimeOutValue)
{
/* extract all the fields but TimeOut field */
UWORD16 value = REG16(RHEA_CNTL_REG_SUPERVISOR_ADDR) & ~RHEA_CNTL_TIMEOUT_MASK;
/* add field contents into register */
REG16(RHEA_CNTL_REG_SUPERVISOR_ADDR) = value | (TimeOutValue << RHEA_BUS_ACCESS_TIMEOUT_POS);
}
/*
-----------------------------------------------------------------------------
NAME : RHEA_ReadControlReg -
-----------------------------------------------------------------------------
*/
void RHEA_ReadCtrolReg(RHEA_AccessFactorStrobe_t *const FactorStrobe0,
RHEA_AccessFactorStrobe_t *const FactorStrobe1,
UWORD8 *const TimeOutValue)
{
UWORD16 memReg = REG16(RHEA_CNTL_REG_USER_ADDR);
*FactorStrobe0 = (RHEA_AccessFactorStrobe_t)(memReg & RHEA_CNTL_FACT_0_MASK);
*FactorStrobe1 = (RHEA_AccessFactorStrobe_t )((memReg & RHEA_CNTL_FACT_1_MASK ) >> RHEA_FACTOR_STROBE1_POS);
*TimeOutValue = (memReg & RHEA_CNTL_TIMEOUT_MASK) >> RHEA_BUS_ACCESS_TIMEOUT_POS;
}
/*
---------------------------------------------------------------------------
RHEA_SetPostedWrite --
---------------------------------------------------------------------------
*/
void RHEA_SetPostedWrite(const WriteBufferStrobe0_t WriteBufferStrobe0,
const WriteBufferStrobe1_t WriteBufferStrobe1)
{
REG16(RHEA_ARM_CONTROL_REG_SUPERVISOR_ADDR)
= ( WriteBufferStrobe0
| WriteBufferStrobe1 << RHEA_WRITE_BUFFER_TOGGLE_STROBE1_POS);
}
/*
----------------------------------------------------------------------------
RHEA_ReadArmRheaCtrolReg --
----------------------------------------------------------------------------
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