📄 io_configuration.c

📁 OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器
💻 C
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void CONFIG_IO_Appli0(void)
{
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0x0);                                                         // set all IO in Mode 0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_ENABLE_OFFSET,MODE1);                  // digitalrf_tx_cs
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_EMIFS_NFBE_0_OFFSET,MODE2);                      // emifs_fadd_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_EMIFS_NFBE_1_OFFSET,MODE2);                      // emifs_fadd_2
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_19_OFFSET,MODE1);                           // emifs_nfcs_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_DATA_OFFSET,MODE1);                    // digitalrf_tx_data
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0xEAEF);                                                      // set all IO to confreg mode value
}
// end CONFIG_IO_Appli0(void)





void CONFIG_IO_Appli1(void)
{
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0x0);                                                         // set all IO in Mode 0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_SPI_DATA_MISO_OFFSET,MODE1);                     // uwire_sdi
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_TE_OFFSET,MODE2);                           // spi_ncs0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_UART3_RX_OFFSET,MODE3);                          // gpio_48
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_4_OFFSET,MODE1);                           // mmc2_dat0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_5_OFFSET,MODE1);                           // mmc2_dat1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_6_OFFSET,MODE1);                           // mmc2_dat2
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_7_OFFSET,MODE1);                           // mmc2_dat3
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_8_OFFSET,MODE1);                           // cam_d_0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_9_OFFSET,MODE1);                           // cam_d_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MMC1_DAT0_OFFSET,MODE1);                         // mcsi1_din
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MMC1_DAT1_OFFSET,MODE1);                         // mcsi1_dout
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MCSI1_DIN_OFFSET,MODE1);                         // usb_1_rcv
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MMC1_DAT2_OFFSET,MODE1);                         // mcsi1_sync
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_TX_CLK_OFFSET,MODE2);                  // digitalrf_sysclkout
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_SPI_CLK_OFFSET,MODE1);                           // uwire_sclk
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ULPDR_ARM_BOOT_EXT_OFFSET,MODE1);                // mcbsp1_clks
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_LCLK_OFFSET,MODE1);                          // mmc2_cmd
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_VS_OFFSET,MODE1);                            // gpio_5
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_UART3_TX_OFFSET,MODE1);                          // uart3_irda_tx
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_TSP_ACT0_OFFSET,MODE1);                          // gpt_event0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_EMIFS_FRDY_OFFSET,MODE2);                        // emifs_nfbaa
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_10_OFFSET,MODE1);                           // spi_ncs1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_12_OFFSET,MODE1);                           // ulpdr_mpu_nreset
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_10_OFFSET,MODE1);                          // cam_d_2
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_11_OFFSET,MODE1);                          // cam_d_3
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_16_OFFSET,MODE3);                           // gpt_event1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_18_OFFSET,MODE1);                           // uwire_nscs1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_19_OFFSET,MODE1);                           // emifs_nfcs_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_SPI_DATA_MOSI_OFFSET,MODE1);                     // uwire_sdo
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_0_OFFSET,MODE2);                       // spi_clk
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_1_OFFSET,MODE2);                       // spi_data_mosi
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_2_OFFSET,MODE2);                       // gpio_24
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_USB_0_RCV_OFFSET,MODE1);                         // uart1_cts
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_HS_OFFSET,MODE1);                            // gpio_3
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MCSI1_DOUT_OFFSET,MODE1);                        // usb_1_txen
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MCSI1_BCLK_OFFSET,MODE1);                        // usb_1_se0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_SPI_NCS0_OFFSET,MODE1);                          // uwire_nscs0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_USB_0_DAT_OFFSET,MODE1);                         // uart1_rx
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_32_OFFSET,MODE1);                           // uart3_irda_select
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_1_OFFSET,MODE2);                            // spi_data_miso
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_2_OFFSET,MODE3);                            // tsp_act1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_USB_0_SE0_OFFSET,MODE1);                         // uart1_tx
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_4_OFFSET,MODE1);                            // gpt_pwm0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_6_OFFSET,MODE1);                            // gpt_pwm1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MMC1_CLK_OFFSET,MODE1);                          // mcsi1_bclk
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_9_OFFSET,MODE1);                            // gpt_ext_clk
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_USB_0_TXEN_OFFSET,MODE1);                        // uart1_rts
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_46_OFFSET,MODE1);                           // uart3_irda_rx
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_47_OFFSET,MODE1);                           // uart3_irda_sd
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_MCSI1_SYNC_OFFSET,MODE1);                        // usb_1_dat
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_XCLK_OFFSET,MODE1);                          // mmc2_clk
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_TEST_NEMU1_OFFSET,MODE5);                        // wire_1
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0xEAEF);                                                      // set all IO to confreg mode value
}
// end CONFIG_IO_Appli1(void)





void CONFIG_IO_Appli2(void)
{
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0x0);                                                         // set all IO in Mode 0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_D_5_OFFSET,MODE3);                           // mcbsp1_fsr
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_ENABLE_OFFSET,MODE1);                  // digitalrf_tx_cs
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_CAM_LCLK_OFFSET,MODE3);                          // mcbsp1_clkr
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_19_OFFSET,MODE1);                           // emifs_nfcs_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_DATA_OFFSET,MODE1);                    // digitalrf_tx_data
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0xEAEF);                                                      // set all IO to confreg mode value
}
// end CONFIG_IO_Appli2(void)





void CONFIG_IO_Appli11(void)
{
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0x0);                                                         // set all IO in Mode 0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_ENABLE_OFFSET,MODE1);                  // digitalrf_tx_cs
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ULPDR_ARM_BOOT_EXT_OFFSET,MODE2);                // nfls_ce2
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_10_OFFSET,MODE2);                           // nfls_ce1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_10_OFFSET,MODE2);                      // nfls_fd2
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_11_OFFSET,MODE2);                      // nfls_fd3
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_13_OFFSET,MODE1);                           // uart2_rts
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_12_OFFSET,MODE2);                      // nfls_fd4
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_13_OFFSET,MODE2);                      // nfls_fd5
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_14_OFFSET,MODE2);                      // nfls_fd6
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_16_OFFSET,MODE1);                           // uart2_cts
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_15_OFFSET,MODE2);                      // nfls_fd7
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_16_OFFSET,MODE2);                      // nfls_cle
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_19_OFFSET,MODE1);                           // emifs_nfcs_1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_17_OFFSET,MODE2);                      // nfls_ale
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_8_OFFSET,MODE2);                       // nfls_fd0
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_ELCD_DATA_9_OFFSET,MODE2);                       // nfls_fd1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_DIGITALRF_DATA_OFFSET,MODE1);                    // digitalrf_tx_data
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_32_OFFSET,MODE1);                           // uart3_irda_select
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_2_OFFSET,MODE3);                            // tsp_act1
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_4_OFFSET,MODE2);                            // nfls_we
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_6_OFFSET,MODE2);                            // nfls_wp
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_8_OFFSET,MODE2);                            // nfls_re
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_9_OFFSET,MODE2);                            // nfls_rdy
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_46_OFFSET,MODE1);                           // uart3_irda_rx
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_GPIO_47_OFFSET,MODE1);                           // uart3_irda_sd
  CONFIG_SetModePin(IO_CONFIGURATION_BASE_ADDR_ARM+IO_CONFIGURATION_CONF_TEST_NEMU1_OFFSET,MODE1);                        // uart3_irda_tx
  SetField32(CONFIGURATION_COMP_MODE_CTRL_0, CONF_MUX_EN_R, 0xEAEF);                                                      // set all IO to confreg mode value
}
// end CONFIG_IO_Appli11(void)
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