rheaswitch.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//========================================================================
//          TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION  
//   Property of Texas Instruments
//   For Unrestricted Internal Use Only
//   Unauthorized reprofuction and/or distribution is strictly prohibited.
//   This product is protected under copyright law and trade secret law
//   as an unpublished work
//   Created 2000,  (C) Copyright 2000 Texas Instruments. All rights reserved
//
//
//   Filename           :rheaswitch.c
//
//   Date of Module Modification:1/2/04
//   Date of Generation :1/2/04
//
//
//========================================================================
#include "rheaswitch.h"

//---------------------------------------------------------------------
// NAME        : RHSW_ARM_TestResetValue
//
// DESCRIPTION : Test the reset values of RHSW_ARM registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void RHSW_ARM_Test_ResetValue(void)
{
  BEGIN_RESET_MODULE();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_MCSI1,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_MCSI1,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_MCSI1,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_MCSI1,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_MCSI2,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_MCSI2,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_MCSI2,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_MCSI2,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_TPU,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_TPU,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_TPU,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_TPU,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_TSP,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_TSP,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_TSP,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_TSP,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_GEA3,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_GEA3,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_GEA3,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_GEA3,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_USIM,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_USIM,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_USIM,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_USIM,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_CNF_CIPHER,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_CIPHER,DSP_PERIPH_LOCK,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_CNF_CIPHER,ARM_PERIPH_LOCK,16);
    END_RESET_TEST();

    BEGIN_RESET_TEST(RHSW_ARM_RHSW_ARM_STA_CIPHER,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_BOTH_LCK_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ITPEND_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_DMAREQ_ERR,16);
    TEST_FIELD_RESET(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ERR_NIRQ,16);
    END_RESET_TEST();

  END_RESET_MODULE();

}

//---------------------------------------------------------------------
// NAME        : RHSW_ARM_TestRegistersAccess
//
// DESCRIPTION : Test the access to RHSW_ARM registers
//
// PARAMETERS  : None
//
// RETURN VALUE: None
//
// LIMITATIONS : None
//---------------------------------------------------------------------
void RHSW_ARM_TestRegistersAccess(void)
{
  BEGIN_ACCESS_MODULE();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_MCSI1,16);
    //RHSW_ARM_RHSW_ARM_CNF_MCSI1,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_MCSI1,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_MCSI1);
    //RHSW_ARM_RHSW_ARM_CNF_MCSI1,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_MCSI1,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_MCSI1);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_MCSI1,16);
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_MCSI1);
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_MCSI1,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_MCSI1);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_MCSI2,16);
    //RHSW_ARM_RHSW_ARM_CNF_MCSI2,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_MCSI2,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_MCSI2);
    //RHSW_ARM_RHSW_ARM_CNF_MCSI2,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_MCSI2,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_MCSI2);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_MCSI2,16);
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_MCSI2);
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_MCSI2,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_MCSI2);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_TPU,16);
    //RHSW_ARM_RHSW_ARM_CNF_TPU,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_TPU,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_TPU);
    //RHSW_ARM_RHSW_ARM_CNF_TPU,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_TPU,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_TPU);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_TPU,16);
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_TPU);
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_TPU,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_TPU);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_TSP,16);
    //RHSW_ARM_RHSW_ARM_CNF_TSP,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_TSP,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_TSP);
    //RHSW_ARM_RHSW_ARM_CNF_TSP,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_TSP,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_TSP);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_TSP,16);
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_TSP);
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_TSP,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_TSP);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_GEA3,16);
    //RHSW_ARM_RHSW_ARM_CNF_GEA3,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_GEA3,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_GEA3);
    //RHSW_ARM_RHSW_ARM_CNF_GEA3,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_GEA3,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_GEA3);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_GEA3,16);
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_GEA3);
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_GEA3,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_GEA3);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_USIM,16);
    //RHSW_ARM_RHSW_ARM_CNF_USIM,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_USIM,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_USIM);
    //RHSW_ARM_RHSW_ARM_CNF_USIM,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_USIM,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_USIM);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_USIM,16);
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_USIM);
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_USIM,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_USIM);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_CNF_CIPHER,16);
    //RHSW_ARM_RHSW_ARM_CNF_CIPHER,DSP_PERIPH_LOCK is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_CNF_CIPHER,ARM_PERIPH_LOCK,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_CNF_CIPHER);
    //RHSW_ARM_RHSW_ARM_CNF_CIPHER,DSP_PERIPH_LOCK is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_CNF_CIPHER,ARM_PERIPH_LOCK,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_CNF_CIPHER);
    END_RW_TEST();

    BEGIN_RW_TEST(RHSW_ARM_RHSW_ARM_STA_CIPHER,16);
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_DMAREQ_ERR is Read Only
    RW_PREPARE_WRITE(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ERR_NIRQ,16);
    RW_WRITE(RHSW_ARM_RHSW_ARM_STA_CIPHER);
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_BOTH_LCK_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ITPEND_ERR is Read Only
    //RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_DMAREQ_ERR is Read Only
    RW_TEST_READ(RHSW_ARM_RHSW_ARM_STA_CIPHER,RHSW_ERR_NIRQ,16);
    RW_WRITE_PREVIOUS_VALUE(RHSW_ARM_RHSW_ARM_STA_CIPHER);
    END_RW_TEST();

  END_ACCESS_MODULE();

}


//--------------------------------------------------------------------------------------
//NAME        : RHEASW_Mcsi1MpuWriteLock
//DESCRIPTION : MPU writes it lock on MODULE_RHEASW register
//PARAMETERS  : None
//RETURN VALUE: None
//--------------------------------------------------------------------------------------
void RHEASW_MpuWriteLock(UWORD16 register_address)
{
  register_address = 0x01;
}  

//--------------------------------------------------------------------------------------
//NAME        : RHEASW_MpuWriteUnlock
//DESCRIPTION : MPU unwrites it lock on MODULE_RHEASW register
//PARAMETERS  : None
//RETURN VALUE: None
//------------------------------------------------------------------------------ 
void RHEASW_MpuWriteUnlock(UWORD16 register_address)
{
  register_address = 0x00;
}  
   
//--------------------------------------------------------------------------------------
//NAME        : RHEASW_MpuReadLock
//DESCRIPTION : MPU reads the MODULE_RHEASW register
//PARAMETERS  : None
//RETURN VALUE: the value of the config register
//------------------------------------------------------------------------------   
UWORD16 RHEASW_MpuReadLock(UWORD16 register_address) 
{
  UWORD16 value;
  value = register_address;
  return value;
}