uartirda.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

//  UIRD_InitScr
//----------------------------------------------------------------------
UWORD8 UIRD_InitScr(const UARTIRDA_DmaModeCtl_t        DmaModeCtl, 
                        const UARTIRDA_DmaMode2_t          DmaMode2, 
                        const UARTIRDA_TxEmptyCtrolIt_t    TxEmptyCtrolIt,
                        const UARTIRDA_RxCtsWakeupEnable_t RxCtsWakeupEnable,
								const UARTIRDA_DSR_It_t            DsrIt,
                        const UARTIRDA_TxTriggranu_t       TxTriggranu,
                        const UARTIRDA_RxTriggranu_t        RxTriggranu)
								
{
 UWORD8 scr_value;

  UARTIRDA_SCR_REG = ( DmaModeCtl             |  
                       DmaMode2          << 1 |  
                       TxEmptyCtrolIt    << 3 |
                       RxCtsWakeupEnable << 4 |
                       DsrIt             << 5 |
							  TxTriggranu <<6|
							  RxTriggranu <<7);
scr_value = UARTIRDA_SCR_REG ;
 
 return scr_value;		  
		  
}







//------------------------------------------
//  UIRD_InitTxfll  (Length)
//-------------------------------------------
void UIRD_InitTxfll(const UWORD8 txfll)
{
   UARTIRDA_TXFLL_REG = txfll;		  
}


//------------------------------------------
//  UIRD_InitTxflh  (Length)
//-------------------------------------------
void UIRD_InitTxflh(const UWORD8 txflh)
{
 UARTIRDA_TXFLH_REG = txflh;		  
}


//------------------------------------------
//  UIRD_InitRxfll  (Length)
//-------------------------------------------
void UIRD_InitRxfll(const UWORD8 rxfll)
{
  UARTIRDA_RXFLL_REG = rxfll;		  
}

//------------------------------------------
//  UIRD_InitRxflh  (Length)
//-------------------------------------------
void UIRD_InitRxflh(const UWORD8 rxflh)
{
  UARTIRDA_RXFLH_REG = rxflh;		  
}



 
//-------------------------------
//    UIRD_InitResume 
//-------------------------------
UWORD8 UIRD_InitResume(void)
{
  return UARTIRDA_RESUME_REG;
}
 
 

//--------------------------------------------------------------
//NAME        : UIRD_InitBlr
//--------------------------------------------------------------
UWORD8 UIRD_InitBlr( const UARTIRDA_XbofType_t        typebof, 
                         const UARTIRDA_StatusFifoReset_t stsfifo )
{
UWORD8 old_lcr, blr_value;
 //Clear LCR[7] to grant access to BLR
 old_lcr = UIRD_ClearLcr7();
 //Setup BLR register
 UARTIRDA_BLR_REG = typebof << 6 | stsfifo <<7 ;
 blr_value        = UARTIRDA_BLR_REG ;
 //Restore LCR
 UARTIRDA_LCR_REG = old_lcr;

 return blr_value;		  
}
		  

//----------------------------------------------
//             UIRD_InitEblr
// WARNING: This register is programmed for
//          future use but is not specified
//          to the customer
//          Its use to provide a max of 6x XBOF 
//----------------------------------------------
UWORD8 UIRD_InitEblr(const UWORD8 nbxbof )
{
UWORD8 eblr_value, old_lcr;
  //Grant Access to EBLR To be confirmed !!!
  old_lcr = UIRD_ClearLcr7();
  //Set EBLR register
  UARTIRDA_EBLR_REG = nbxbof;	  
  eblr_value        = UARTIRDA_EBLR_REG ;
  //Restore LCR
  UARTIRDA_LCR_REG = old_lcr;
 
  return eblr_value;		  
}



//-------------------------------------------------
//             UIRD_InitAdr1
//-------------------------------------------------
UWORD8 UIRD_InitAdr1(const UWORD8 adr1)
{
UWORD8 adr1_value, lcr_old;

  //Store current LCR value and Set LCR to 0xBF
  lcr_old = UIRD_SetBfToLcr();

  //Initialize adr1/xon1 and read it back
  UARTIRDA_ADR1_REG = adr1;  
  adr1_value =  UARTIRDA_ADR1_REG ;
 
  //Restore LCR value
  UARTIRDA_LCR_REG = lcr_old;
 
  return adr1_value;		  
}


//--------------------------------------------
//  UIRD_InitAdr2
//--------------------------------------------
UWORD8 UIRD_InitAdr2(const UWORD8 adr2)
{ 
UWORD8 adr2_value, lcr_old;

  //Set LCR to grant access to ADR2
  lcr_old = UIRD_SetBfToLcr();

  //Store current LCR value and Set LCR to 0xBF
  lcr_old          =  UARTIRDA_LCR_REG;
  UARTIRDA_LCR_REG = 0xBF;
 
  //Initialize adr2/xon2 and read it back
  UARTIRDA_ADR2_REG = adr2;
  adr2_value        = UARTIRDA_ADR2_REG;
                             
  //Restore LCR value
  UARTIRDA_LCR_REG= lcr_old ;
 
  return adr2_value;		  
}





//---------------------------------------------------------------------
//   Initialise  Auxiliary Control Register
//-----------------------------------------------------------------
UWORD8 UIRD_InitAcreg(const UARTIRDA_EotEn_t      eot, 
                          const UARTIRDA_AbortEn_t    abort, 
                          const UARTIRDA_SctxEn_t     sctx ,
                          const UARTIRDA_LongStop_t   longstop,
                          const UARTIRDA_rxir_input_t duplexmode,
                          const UARTIRDA_SdMod_t      sdmode, 
                          const UARTIRDA_PulseType_t  pulse)
{
UWORD8  old_lcr;
UWORD8  acreg_value;
 
  //Set LCR to granmt access to ACREG
  old_lcr =  UIRD_ClearLcr7();  

  UARTIRDA_ACREG_REG = (   eot 
                         | abort      << 1 
                         | sctx       << 2 
                         | longstop   << 4 
                         | duplexmode << 5 
                         | sdmode     << 6 
                         | pulse      << 7);	  
  acreg_value = UARTIRDA_ACREG_REG;

 //Restore old value of LCR
 UARTIRDA_LCR_REG = old_lcr;

 return acreg_value;		  		  
}


//--------------------------------------------------------
//  UIRD_RxFifoIsNotEmptyUartMode                    -
//  field pos 1: RX_FIFO_E = 1 => EMPTY                  -
//                         = 0 => AT LEAST ONE CHARACTER -
//--------------------------------------------------------
boolean_t UIRD_RxFifoIsNotEmptyUartMode(void)
{
UWORD8    old_lcr;
boolean_t not_empty;
  //Clear LCR[7] to grant access to LSR
  old_lcr = UIRD_ClearLcr7();
  //Evaluate if  not empty
  not_empty = (boolean_t) (UARTIRDA_LSR_REG & 0x01);
  //Restore LCR
  UARTIRDA_LCR_REG = old_lcr;
  return not_empty;
}




//--------------------------------------------------------
//  UIRD_RxFifoIsNotEmptySirMode                     -
//  field pos 1: RX_FIFO_E = 1 => EMPTY                  -
//                         = 0 => AT LEAST ONE CHARACTER -
//--------------------------------------------------------
boolean_t UIRD_RxFifoIsNotEmptySirMode(void)
{
UWORD8    old_lcr;
boolean_t empty, not_empty;
  //Clear LCR[7] to grant access to LSR
  old_lcr = UIRD_ClearLcr7();
  //Evaluate if  not empty
  empty = (boolean_t) (UARTIRDA_LSR_REG & 0x01);
  //Restore LCR
  UARTIRDA_LCR_REG = old_lcr;
  if (empty == True) not_empty = False;
  else if (empty == False) not_empty = True;
  return not_empty;
}


//----------------------------------------------------
//  UIRD_IsTransmitAndHoldRegNotEmpty            -
//----------------------------------------------------
UWORD8 UIRD_IsTransmitAndHoldRegNotEmpty(void)
{
UWORD8 not_empty, old_lcr;

  //Clear LCR[7] to grant access to LSR
  old_lcr = UIRD_ClearLcr7();
  //Evaluate if  not empty
  not_empty = ! ( (UARTIRDA_LSR_REG & UARTIRDA_LSR_EMPTY1) >> 6 );
  //Restore LCR
  UARTIRDA_LCR_REG = old_lcr;

  return not_empty;
}


   
//--------------------------------------
//          UIRD_ReadSfregl
//---------------------------------------
UWORD8 UIRD_ReadSfregl(void)
{
  return  UARTIRDA_SFREGL_REG;
}
 
 
//--------------------------------------
//          UIRD_ReadSfregh
//--------------------------------------- 
UWORD8 UIRD_ReadSfregh(void)
{
  return  UARTIRDA_SFREGH_REG;
}



//-------------------------------------
//         UIRD_InitDiv16
//--------------------------------------
UWORD8 UIRD_InitDiv16(const UWORD8 div16)
{
UWORD8 lcr_old, div16_value;
  //Set LCR to 0xBF to grant access to div16
  lcr_old = UIRD_SetBfToLcr();
  //Write into DIV16 register and read back its value
  UARTIRDA_DIV16_REG = div16;	  
  div16_value        = UARTIRDA_DIV16_REG;
  //Restore LCR value
  UARTIRDA_LCR_REG = lcr_old;

  return div16_value;		  		  
}




		  
 
//-----------------------------------------------------------
//                     UIRD_InitTlr
//-----------------------------------------------------------
UWORD8 UIRD_InitTlr(const UARTIRDA_TxFifoTrigDma_t txtrigdma, 
                        const UARTIRDA_RxFifoTrigDma_t rxtrigdma)
{ 
UWORD8 old_efr, old_mcr, triglevel;
  //Set register to grant access to TCR
  old_efr = UIRD_SetEfr4();
  old_mcr = UIRD_SetMcr6();
  //Set TLR and read it back
  UARTIRDA_TLR_REG = txtrigdma |  rxtrigdma << 4;		
  triglevel        = UARTIRDA_TLR_REG ;	
  //Restore access registers
  UIRD_RestoreEfr(old_efr);
  UIRD_RestoreMcr(old_mcr);		
  
  return triglevel;
}




//--------------------------------------------------------
//                 UIRD_TestRegisters
//--------------------------------------------------------
UWORD16 UIRD_TestRegisters(void)
{
UWORD16 val;
UWORD16  err = RES_OK;

  //UIR test reset value
//FOR SAMSON ONLY   val = UIRD_ReadUIR() & UARTIRDA_UIR_REG_MASK;
//FOR SAMSON ONLY   if ( val != UARTIRDA_UIR_REG_RESET_VALUE )
//FOR SAMSON ONLY   {
//FOR SAMSON ONLY      RES_Set(UARTIRDA_UIR_REG_RESET_ERROR);
//FOR SAMSON ONLY      RES_Set(val);
//FOR SAMSON ONLY      err = RES_BAD;
//FOR SAMSON ONLY   }
  
  //IER test reset value
  val = UIRD_ReadIer();
  if ( val != UARTIRDA_IER_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_IER_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //IIR test reset value
  val = UIRD_ReadIir();
  if ( val != UARTIRDA_IIR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_IIR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //FCR is Writable only so Read reset value is impossible

  //EFR test reset value
  val = UIRD_ReadEfr();
  if ( val != UARTIRDA_EFR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_EFR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //LCR test reset value
  val = UIRD_ReadLcr();
  if ( val != UARTIRDA_LCR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_LCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //MCR test reset value
  val = UIRD_ReadMcr();
  if ( val != UARTIRDA_MCR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_MCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //XON1/ADDR1 undefined on reset

  //LSR test reset value
  val = UIRD_Readlsr() & UARTIRDA_LSR_REG_RESET_MASK;
  if ( val != UARTIRDA_LSR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_LSR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }


  //XON2/ADDR2 undefined on reset

  //MSR Reset value not tested since the test bench
  //Set The first bit 0 to 1 for the external loop

  //TCR test reset value
  val = UIRD_ReadTcr();
  if ( val != UARTIRDA_TCR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_TCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //XOFF1, XOFF2, SPR   are undefined on reset

  //TLR  test reset value
  val = UIRD_ReadTlr();
  if ( val != UARTIRDA_TLR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_TLR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }


  //MDR1  test reset value
  val = UIRD_ReadMdr1() & UARTIRDA_MDR1_REG_RESET_MASK;
  if ( val != UARTIRDA_MDR1_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_MDR1_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }


 

  //SCR  test reset value
  val = UIRD_ReadScr();
  if ( val != UARTIRDA_SCR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_SCR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

  //SSR  test reset value
  val = UIRD_ReadSsr();
  if ( val != UARTIRDA_SSR_REG_RESET_VALUE )
  {
     RES_Set(UARTIRDA_SSR_REG_RESET_ERROR);
     RES_Set(val);
     err = RES_BAD;
  }

 
  return err;
}
 
 
 
 


//  UIRD_TxFifoIsFull            -
//---------------------------------------
boolean_t UIRD_TxFifoIsFull(void)
{
  return (boolean_t) (UARTIRDA_SSR_REG & 1);
}