📄 uartirda.c
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/*
===============================================================================
TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
Property of Texas Instruments
For Unrestricted Internal Use Only
Unauthorized reproduction and/or distribution is strictly prohibited.
This product is protected under copyright law and trade secret law
as an unpublished work.
Created 1999, (C) Copyright 1999 Texas Instruments. All rights reserved.
Filename : uartirda_a9.c
Description : Header file for the UART IrDA connected to ARM9
Project : Perseus
Author : Sebastien Sabatier
===============================================================================
*/
#include "uartirda.h"
//--------------------------------------------------
// REGISTERS MASK -
//--------------------------------------------------
//RHR and THR are undefined on reset
//UIR
//FOR SAMSON ONLY #define UARTIRDA_UIR_REG_RESET_VALUE 0x00
//FOR SAMSON ONLY #define UARTIRDA_UIR_REG_MASK 0x03
#define UARTIRDA_FCR_REG_RESET_VALUE 0x00
#define UARTIRDA_FCR_REG_RESET_MASK 0x00FF
#define UARTIRDA_SCR_REG_RESET_VALUE 0x00
#define UARTIRDA_SCR_REG_RESET_MASK 0x001F
#define UARTIRDA_LCR_REG_RESET_VALUE 0x00
#define UARTIRDA_LCR_REG_RESET_MASK 0x00FF
//LSR mode SIR
#define UARTIRDA_LSR_REG_RESET_VALUE 0x60
#define UARTIRDA_LSR_REG_RESET_MASK 0x00E3
//SSR
#define UARTIRDA_SSR_REG_RESET_VALUE 0x00
#define UARTIRDA_SSR_REG_RESET_MASK 0x0003
//MCR
#define UARTIRDA_MCR_REG_RESET_VALUE 0x00
#define UARTIRDA_MCR_REG_RESET_MASK 0x00FF
//MSR
#define UARTIRDA_MSR_REG_RESET_VALUE 0x00
#define UARTIRDA_MSR_REG_RESET_MASK 0x00EF
//IER
#define UARTIRDA_IER_REG_RESET_VALUE 0x00
#define UARTIRDA_IER_REG_RESET_MASK 0x00FF
//IIR
#define UARTIRDA_IIR_REG_RESET_VALUE 0x01
#define UARTIRDA_IIR_REG_RESET_MASK 0x00FF
//EFR
#define UARTIRDA_EFR_REG_RESET_VALUE 0x00
#define UARTIRDA_EFR_REG_RESET_MASK 0x00FF
//XON1/ADDR1, XON2/ADDR2, XOFF1, XOFF2, SPR, DLL, DLH UNDEFINED on reset
//TCR
#define UARTIRDA_TCR_REG_RESET_VALUE 0x0F
#define UARTIRDA_TCR_REG_RESET_MASK 0x00FF
//TLR
#define UARTIRDA_TLR_REG_RESET_VALUE 0x00
#define UARTIRDA_TLR_REG_RESET_MASK 0x00FF
//MDR1
#define UARTIRDA_MDR1_REG_RESET_VALUE 0x07
#define UARTIRDA_MDR1_REG_RESET_MASK 0x00AF
//MDR2
#define UARTIRDA_MDR2_REG_RESET_VALUE 0x00
#define UARTIRDA_MDR2_REG_RESET_MASK 0x0006
//TXFL
#define UARTIRDA_TXFLL_REG_RESET_VALUE 0x00
#define UARTIRDA_TXFLL_REG_RESET_MASK 0x00FF
#define UARTIRDA_TXFLH_REG_RESET_VALUE 0x00
#define UARTIRDA_TXFLH_REG_RESET_MASK 0x001F
//RXFL
#define UARTIRDA_RXFLL_REG_RESET_VALUE 0x00
#define UARTIRDA_RXFLL_REG_RESET_MASK 0x00FF
#define UARTIRDA_RXFLH_REG_RESET_VALUE 0x00
#define UARTIRDA_RXFLH_REG_RESET_MASK 0x000F
//SFLSR and SFREGL are undefined on reset
//RESUME
#define UARTIRDA_RESUME_REG_RESET_VALUE 0x00
#define UARTIRDA_RESUME_REG_RESET_MASK 0x00FF
//BLR
#define UARTIRDA_BLR_REG_RESET_VALUE 0x40
#define UARTIRDA_BLR_REG_RESET_MASK 0x00FF
#define UARTIRDA_DIV16_REG_RESET_VALUE 0x00
#define UARTIRDA_DIV16_REG_RESET_MASK 0x00FF
//ACREG
#define UARTIRDA_ACREG_RESET_VALUE 0x00
#define UARTIRDA_ACREG_RESET_MASK 0x00C7
//####################################################################################################
///* ---- UARTIRDA Configuration FIFO Control Register(FCR) --- **
//####################################################################################################
#define UARTIRDA_FCR_FIFO_D 0x00 //Disable Rx and Tx FIFO
#define UARTIRDA_FCR_FIFO_E 0x01 //Enable Rx and Tx FIFO
#define UARTIRDA_FCR_FIFO_NO 0x00 //No change
#define UARTIRDA_FCR_FIFO_CLR 0x01 // Clears FIFO
#define UARTIRDA_FCR_FIFO_MODE0 0x00 //DMA mode 0
#define UARTIRDA_FCR_FIFO_MODE1 0x01 //DMA mode 1
#define UARTIRDA_FCR_FIFO_TRIGTX8 0x00 //trigger TX FIFO level
#define UARTIRDA_FCR_FIFO_TRIGTX16 0x01
#define UARTIRDA_FCR_FIFO_TRIGTX32 0x02
#define UARTIRDA_FCR_FIFO_TRIGTX56 0x03
#define UARTIRDA_FCR_FIFO_TRIGRX8 0x00 //trigger RX FIFO level
#define UARTIRDA_FCR_FIFO_TRIGRX16 0x01
#define UARTIRDA_FCR_FIFO_TRIGRX56 0x02
#define UARTIRDA_FCR_FIFO_TRIGRX60 0x03
//####################################################################################################
///* ---- UARTIRDA SUPPLEMENTARY CONTROL Register(SCR) --- **
//####################################################################################################
#define UARTIRDA_SCR_DMA_CLT0 0x00 //DMA mode set with FCR[3]
#define UARTIRDA_SCR_DMA_CLT1 0x01 //DMA mode set with SCR Register
#define UARTIRDA_SCR_DMA_MOD0 0x00 //DMA mode 0
#define UARTIRDA_SCR_DMA_MOD1 0x01 //DMA mode 01
#define UARTIRDA_SCR_DMA_MOD2 0x02 //DMA mode 02
#define UARTIRDA_SCR_DMA_MOD3 0x03 //DMA mode 03
#define UARTIRDA_SCR_TX_CTLIT0 0x00 //mode normal for THR interrupt
#define UARTIRDA_SCR_TX_CTLIT1 0x00 //THR interrupt TX FIFO and Shift empty
//####################################################################################################
///* ---- UARTIRDA Configuration Line Control Register(LCR) --- **
//####################################################################################################
// UARTIRDA Character length
#define UARTIRDA_LCR_LENGTH_CHAR5 0x00 // Transmiter or Receiver
#define UARTIRDA_LCR_LENGTH_CHAR6 0x01
#define UARTIRDA_LCR_LENGTH_CHAR7 0x02
#define UARTIRDA_LCR_LENGTH_CHAR8 0x03
// UARTIRDA Stop bit
#define UARTIRDA_LCR_STOP1 0x00 // Any word length
#define UARTIRDA_LCR_STOP15 0x01 // Only word length CHAR5
#define UARTIRDA_LCR_STOP2 0x01 // word length CHAR6, CHAR7,CHAR8
// UARTIRDA PARITY
#define UARTIRDA_LCR_NPA 0x00 //no parity
#define UARTIRDA_LCR_PA 0x01 // parity
// UARTIRDA PARITY TYPE1
#define UARTIRDA_LCR_PA_TYPE1O 0x00 // parity odd
#define UARTIRDA_LCR_PA_TYPE1E 0x01 // parity even
// UARTIRDA PARITY TYPE2
#define UARTIRDA_LCR_PA_TYPE2H 0x00 // parity force to 1
#define UARTIRDA_LCR_PA_TYPE2L 0x01 // parity force to 0
// UARTIRDA BREAK ENABLE
#define UARTIRDA_LCR_BREAK0 0x00 //Normal operation
#define UARTIRDA_LCR_BREAK1 0x01 //BREAK mode
// UARTIRDA BREAK ENABLE
#define UARTIRDA_LCR_DIV0 0x00 //Normal operation
#define UARTIRDA_LCR_DIV1 0x01 //Divisor Enable
//###################################################################################################
///* ---- UARTIRDA FIFO Control Register --- **
//###################################################################################################
// UARTIRDA FIFO TX trigger level length
#define UARTIRDA_TX_FIFO8 0x00 // Transmiter
#define UARTIRDA_TX_FIFO16 0x01
#define UARTIRDA_TX_FIFO32 0x02
#define UARTIRDA_TX_FIFO56 0x03
// UARTIRDA FIFO RX trigger level length
#define UARTIRDA_RX_FIFO8 0x00 // Receiver
#define UARTIRDA_RX_FIFO16 0x01
#define UARTIRDA_RX_FIFO56 0x02
#define UARTIRDA_RX_FIFO60 0x03
//###################################################################################################
///* ----- UARTIRDA Line Status register --- **
//###################################################################################################
#define UARTIRDA_LSR_RCV0 0x00 // RX FIFO
#define UARTIRDA_LSR_OVR0 0x00 // OVERUN ERROR
#define UARTIRDA_LSR_PARITY0 0x00 // PARYTY ERROR
#define UARTIRDA_LSR_FRAM0 0x00 // FRAMMING ERROR
#define UARTIRDA_LSR_BREAK0 0x00 // BREAK CONDITION
#define UARTIRDA_LSR_TX_HOLD0 0x00 // HOLD REGISTER EMPTY
#define UARTIRDA_LSR_EMPTY0 0x00 // HOLD AND SHIFT REGISTER EMPTY
#define UARTIRDA_LSR_FIFO_ERROR0 0x00 // NORMAL OPERATION
// +++ MASK for Line Status register +++
#define UARTIRDA_LSR_RCV1 0x01 // RX FIFO
#define UARTIRDA_LSR_OVR1 0x02 // OVERUN ERROR
#define UARTIRDA_LSR_PARITY1 0x04 // PARYTY ERROR
#define UARTIRDA_LSR_FRAM1 0x08 // FRAMMING ERROR
#define UARTIRDA_LSR_BREAK1 0x10 // BREAK CONDITION
#define UARTIRDA_LSR_TX_HOLD1 0x20 // HOLD REGISTER EMPTY
#define UARTIRDA_LSR_EMPTY1 0x40 // HOLD AND SHIFT REGISTER EMPTY
#define UARTIRDA_LSR_FIFO_ERROR1 0x80 // NORMAL OPERATION
//---------------------------------------------
// IER Interrupt Enable REGISTER -
//---------------------------------------------
//SIR mode
#define UARTIRDA_SIR_IER_THR_IT_POSBIT 1
#define UARTIRDA_SIR_IER_LAST_RX_BYTE_IT_POSBIT 2
#define UARTIRDA_SIR_IER_RX_OVERRUN_IT_POSBIT 3
#define UARTIRDA_SIR_IER_STS_FIFO_TRIG_IT_POSBIT 4
#define UARTIRDA_SIR_IER_TX_UNDERRUN_IT_POSBIT 5
#define UARTIRDA_SIR_IER_LINE_STS_IT_POSBIT 6
#define UARTIRDA_SIR_IER_EOF_IT_POSBIT 7
//------------------------------------------
// UIRD_SetBfToLcr
//------------------------------------------
UWORD8 UIRD_SetBfToLcr(void)
{
UWORD8 LCR_Storedvalue = UARTIRDA_LCR_REG;
UARTIRDA_LCR_REG = 0xBF;
return LCR_Storedvalue;
}
//--------------------------------------------------------------------
// UIRD_ClearLcr7
//--------------------------------------------------------------------
UWORD8 UIRD_ClearLcr7(void)
{
UWORD8 oldlcr;
oldlcr = UARTIRDA_LCR_REG;//Store LCR
UARTIRDA_LCR_REG &= 0x7F; //Clear LCR[7]
return oldlcr; //return the previous lcr
}
//--------------------------------------------------------------------
// UIRD_SetEfr4
//--------------------------------------------------------------------
UWORD8 UIRD_SetEfr4(void)
{
UWORD8 efr4, efrold, lcrold;
//To access EFR
lcrold=UIRD_SetBfToLcr();
//Store old value EFR register & Set bit EFR[4]
efrold= UARTIRDA_EFR_REG;
efr4=efrold | 0x10;
UARTIRDA_EFR_REG = efr4;
//Restore LCR
UARTIRDA_LCR_REG=lcrold;
//Return previous efr value
return efrold;
}
//--------------------------------------------------------------------
// UIRD_ClearEfr4
//--------------------------------------------------------------------
UWORD8 UIRD_ClearEfr4(void)
{
UWORD8 efr4, efrold, lcrold;
//Set LCR to 0xBF To access EFR
lcrold=UIRD_SetBfToLcr();
//Store old value EFR & Clear EFR[4]
efrold= UARTIRDA_EFR_REG;
efr4 =efrold & 0xEF;
UARTIRDA_EFR_REG = efr4;
//Restore LCR
UARTIRDA_LCR_REG=lcrold;
//Return previous efr value
return efrold;
}
//--------------------------------------------------------------------
// UIRD_RestoreEfr
//--------------------------------------------------------------------
void UIRD_RestoreEfr(const UWORD8 value)
{
//To access EFR
UWORD8 lcrold=UIRD_SetBfToLcr();
//Update EFR value
UARTIRDA_EFR_REG = value;
//Restore LCR
UARTIRDA_LCR_REG=lcrold;
}
//--------------------------------------------------------------------
// UIRD_SetMcr6
//--------------------------------------------------------------------
UWORD8 UIRD_SetMcr6(void)
{
UWORD8 efrold, lcrold, mcrold, mcr6;
//Set registers access
efrold = UIRD_SetEfr4();
lcrold = UIRD_ClearLcr7();
//Set bit MCR[6] =1
mcrold = UARTIRDA_MCR_REG;
mcr6 = mcrold | 0x40;
UARTIRDA_MCR_REG = mcr6;
//Restore registers access
UIRD_RestoreEfr(efrold);
UARTIRDA_LCR_REG=lcrold;
//Return previous MCR value for restore further
return mcrold;
}
//--------------------------------------------------
// UIRD_RestoreMcr
//--------------------------------------------------
void UIRD_RestoreMcr(const UWORD8 mcr)
{
UWORD8 efrold, lcrold;
//Set registers to access MCR
efrold = UIRD_SetEfr4();
lcrold = UIRD_ClearLcr7();
//Restore MCR
UARTIRDA_MCR_REG = mcr;
//Restore registers access
UIRD_RestoreEfr(efrold);
UARTIRDA_LCR_REG=lcrold;
}
//---------------------------------------------------------------------
// UIRD_InitFcr: Initialise FIFO Control Register) write only
//---------------------------------------------------------------------
void UIRD_InitFcr(UARTIRDA_FifoEnable_t EnFifo ,
UARTIRDA_RxFifoClear_t ClRxFifo,
UARTIRDA_TxFifoClear_t ClTxFifo,
UARTIRDA_DmaMode_t DmaMode,
UARTIRDA_TxFifoTrigger_t TxnbFifo,
UARTIRDA_RxFifoTrigger_t RxnbFifo)
{
UWORD8 efrold, lcrold;
//Set registers to access FCR
efrold = UIRD_SetEfr4();
lcrold = UIRD_ClearLcr7();
UARTIRDA_FCR_REG = (EnFifo | ClRxFifo << 1 | ClTxFifo << 2 |
DmaMode << 3 | TxnbFifo << 4 | RxnbFifo << 6);
//restore registers old value
UIRD_RestoreEfr(efrold);
UARTIRDA_LCR_REG = lcrold;
}
//--------------------------------------------------------------------
// UIRD_InitLcr: Initialise Line Control Register
//--------------------------------------------------------------------
UWORD8 UIRD_InitLcr(const UARTIRDA_CharLength_t CharLength,
const UARTIRDA_NbStop_t nbStop,
const UARTIRDA_ParityEnable_t ParityEnable,
const UARTIRDA_ParityType_t ParityType,
const UARTIRDA_BreakEnable_t BreakEnable,
const UARTIRDA_DivisorEnable_t DivisorEnable)
{
UARTIRDA_LCR_REG = ( CharLength |
nbStop << 2 |
ParityEnable << 3 |
ParityType << 4 |
BreakEnable << 6 |
DivisorEnable << 7);
return UARTIRDA_LCR_REG;
}
//-------------------------------------------------------------------
// UIRD_InitMcr
//-------------------------------------------------------------------
void UIRD_InitMcr(const UARTIRDA_Dcd_t Dcd,
const UARTIRDA_Rts_t Rts,
const UARTIRDA_LoopBackEnable_t LoopbackEnable,
const UARTIRDA_Xon_t Xon,
const UARTIRDA_TcrTlr_t TcrTlr,
const UARTIRDA_ClkSel_t ClkSel)
{
UWORD8 efrold, lcrold;
//Set registers to access MCR
efrold = UIRD_SetEfr4();
lcrold = UIRD_ClearLcr7();
UARTIRDA_MCR_REG = ( Dcd | Rts << 1 | LoopbackEnable << 4
| Xon << 5 | TcrTlr << 6 | ClkSel << 7);
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