emifs.c

OMAP1030 处理器的ARM 侧硬件测试代码 OMAP1030 是TI的双核处理器

  /* Read the config register */
  tmp = *(UWORD32*)EMIFS_CONFIG_REG;

  /* Assign the PDE value */
  tmp &= ~EMIFS_GLOBAL_PWD_EN_MSK;
  tmp |= (PDE << EMIFF_GLOBAL_PWD_EN_BITPOS);

  /* Assign the PWD_EN value */
  tmp &= ~EMIFS_PWD_EN_MSK;
  tmp |= (PWD_EN << EMIFF_PWD_EN_BITPOS);

  /* Assign the WP value */
  tmp &= ~EMIFS_WR_PROTECT_EN_MSK;
  tmp |= (WP << EMIFF_WR_PROTECT_EN_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_CONFIG_REG = tmp;
}



//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigCs0Pgwsten
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigCs0Pgwsten (	UWORD8 PGWSTEN,
				UWORD8 PGWST)
{
  UWORD32 tmp;

  /* Read the nCS0 config register */
  tmp = *(UWORD32*)EMIFS_nCS0_CONFIG_REG;

  /* Assign the PGWST value */
  tmp &= ~EMIFS_CS0_NEW_PGWST_MSK;
  tmp |= (PGWST << EMIFS_CS0_NEW_PGWST_BITPOS);

  /* Assign the PGWSTEN value */
  tmp &= ~EMIFS_CS0_PGWSTEN_MSK;
  tmp |= (PGWSTEN << EMIFS_CS0_PGWSTEN_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS0_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigCs1Pgwsten
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigCs1Pgwsten (	UWORD8 PGWSTEN,
				UWORD8 PGWST)
{
  UWORD32 tmp;

  /* Read the nCS1 config register */
  tmp = *(UWORD32*)EMIFS_nCS1_CONFIG_REG;

  /* Assign the PGWST value */
  tmp &= ~EMIFS_CS1_NEW_PGWST_MSK;
  tmp |= (PGWST << EMIFS_CS1_NEW_PGWST_BITPOS);

  /* Assign the PGWSTEN value */
  tmp &= ~EMIFS_CS1_PGWSTEN_MSK;
  tmp |= (PGWSTEN << EMIFS_CS1_PGWSTEN_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS1_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigCs2Pgwsten
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigCs2Pgwsten (	UWORD8 PGWSTEN,
				UWORD8 PGWST)
{
  UWORD32 tmp;

  /* Read the nCS2 config register */
  tmp = *(UWORD32*)EMIFS_nCS2_CONFIG_REG;

  /* Assign the PGWST value */
  tmp &= ~EMIFS_CS2_NEW_PGWST_MSK;
  tmp |= (PGWST << EMIFS_CS2_NEW_PGWST_BITPOS);

  /* Assign the PGWSTEN value */
  tmp &= ~EMIFS_CS2_PGWSTEN_MSK;
  tmp |= (PGWSTEN << EMIFS_CS2_PGWSTEN_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS2_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigCs3Pgwsten
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigCs3Pgwsten (	UWORD8 PGWSTEN,
				UWORD8 PGWST)
{
  UWORD32 tmp;

  /* Read the nCS3 config register */
  tmp = *(UWORD32*)EMIFS_nCS3_CONFIG_REG;

  /* Assign the PGWST value */
  tmp &= ~EMIFS_CS3_NEW_PGWST_MSK;
  tmp |= (PGWST << EMIFS_CS3_NEW_PGWST_BITPOS);

  /* Assign the PGWSTEN value */
  tmp &= ~EMIFS_CS3_PGWSTEN_MSK;
  tmp |= (PGWSTEN << EMIFS_CS3_PGWSTEN_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS3_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigAdvCs0Reg
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigAdvCs0Reg (	UWORD8 OESETUP,
				UWORD8 OEHOLD,
				UWORD8 ADVHOLD,
				UWORD8 BTMODE)
{
  UWORD32 tmp;

  /* Read the nCS0 config register */
  tmp = *(UWORD32*)EMIFS_ADV_nCS0_CONFIG_REG;

  /* Assign the OESETUP value */
  tmp &= ~EMIFS_ADV_nCS0_OESETUP_BIT_MASK;
  tmp |= (OESETUP << EMIFS_ADV_nCS0_OESETUP_BITPOS);

  /* Assign the OEHOLD value */
  tmp &= ~EMIFS_ADV_nCS0_OEHOLD_BIT_MASK;
  tmp |= (OEHOLD << EMIFS_ADV_nCS0_OEHOLD_BITPOS);

  /* Assign the ADVHOLD value */
  tmp &= ~EMIFS_ADV_nCS0_ADVHOLD_BIT_MASK;
  tmp |= (ADVHOLD << EMIFS_ADV_nCS0_ADVHOLD_BITPOS);

  /* Assign the BTMODE value */
  tmp &= ~EMIFS_ADV_nCS0_BTMODE_BIT_MASK;
  tmp |= (BTMODE << EMIFS_ADV_nCS0_BTMODE_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_ADV_nCS0_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigAdvCs1Reg
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigAdvCs1Reg (	UWORD8 OESETUP,
				UWORD8 OEHOLD,
				UWORD8 ADVHOLD,
				UWORD8 BTMODE)
{
  UWORD32 tmp;

  /* Read the nCS1 config register */
  tmp = *(UWORD32*)EMIFS_ADV_nCS1_CONFIG_REG;

  /* Assign the OESETUP value */
  tmp &= ~EMIFS_ADV_nCS1_OESETUP_BIT_MASK;
  tmp |= (OESETUP << EMIFS_ADV_nCS1_OESETUP_BITPOS);

  /* Assign the OEHOLD value */
  tmp &= ~EMIFS_ADV_nCS1_OEHOLD_BIT_MASK;
  tmp |= (OEHOLD << EMIFS_ADV_nCS1_OEHOLD_BITPOS);

  /* Assign the ADVHOLD value */
  tmp &= ~EMIFS_ADV_nCS1_ADVHOLD_BIT_MASK;
  tmp |= (ADVHOLD << EMIFS_ADV_nCS1_ADVHOLD_BITPOS);

  /* Assign the BTMODE value */
  tmp &= ~EMIFS_ADV_nCS1_BTMODE_BIT_MASK;
  tmp |= (BTMODE << EMIFS_ADV_nCS1_BTMODE_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_ADV_nCS1_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigAdvCs2Reg
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigAdvCs2Reg (	UWORD8 OESETUP,
				UWORD8 OEHOLD,
				UWORD8 ADVHOLD,
				UWORD8 BTMODE)
{
  UWORD32 tmp;

  /* Read the nCS2 config register */
  tmp = *(UWORD32*)EMIFS_ADV_nCS2_CONFIG_REG;

  /* Assign the OESETUP value */
  tmp &= ~EMIFS_ADV_nCS2_OESETUP_BIT_MASK;
  tmp |= (OESETUP << EMIFS_ADV_nCS2_OESETUP_BITPOS);

  /* Assign the OEHOLD value */
  tmp &= ~EMIFS_ADV_nCS2_OEHOLD_BIT_MASK;
  tmp |= (OEHOLD << EMIFS_ADV_nCS2_OEHOLD_BITPOS);

  /* Assign the ADVHOLD value */
  tmp &= ~EMIFS_ADV_nCS2_ADVHOLD_BIT_MASK;
  tmp |= (ADVHOLD << EMIFS_ADV_nCS2_ADVHOLD_BITPOS);

  /* Assign the BTMODE value */
  tmp &= ~EMIFS_ADV_nCS2_BTMODE_BIT_MASK;
  tmp |= (BTMODE << EMIFS_ADV_nCS2_BTMODE_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_ADV_nCS2_CONFIG_REG = tmp;
}


//-----------------------------------------------------------------------------
// NAME         : EMIF_ConfigAdvCs3Reg
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_ConfigAdvCs3Reg (	UWORD8 OESETUP,
				UWORD8 OEHOLD,
				UWORD8 ADVHOLD,
				UWORD8 BTMODE)
{
  UWORD32 tmp;

  /* Read the nCS3 config register */
  tmp = *(UWORD32*)EMIFS_ADV_nCS3_CONFIG_REG;

  /* Assign the OESETUP value */
  tmp &= ~EMIFS_ADV_nCS3_OESETUP_BIT_MASK;
  tmp |= (OESETUP << EMIFS_ADV_nCS3_OESETUP_BITPOS);

  /* Assign the OEHOLD value */
  tmp &= ~EMIFS_ADV_nCS3_OEHOLD_BIT_MASK;
  tmp |= (OEHOLD << EMIFS_ADV_nCS3_OEHOLD_BITPOS);

  /* Assign the ADVHOLD value */
  tmp &= ~EMIFS_ADV_nCS3_ADVHOLD_BIT_MASK;
  tmp |= (ADVHOLD << EMIFS_ADV_nCS3_ADVHOLD_BITPOS);

  /* Assign the BTMODE value */
  tmp &= ~EMIFS_ADV_nCS3_BTMODE_BIT_MASK;
  tmp |= (BTMODE << EMIFS_ADV_nCS3_BTMODE_BITPOS);

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_ADV_nCS3_CONFIG_REG = tmp;
}



//-----------------------------------------------------------------------------
// NAME         : EMIF_Cs3Fclkdiv
//
// RETURN VALUE : None
//               
// LIMITATIONS  : None
// ----------------------------------------------------------------------------

void EMIF_Cs3Fclkdiv (UWORD8 FCLKDIV )
{
  UWORD32 tmp;

  /* Read the nCS3 config register */
  tmp = *(UWORD32*)EMIFS_nCS3_CONFIG_REG;

  /* Assign the FCLKDIV value */
  tmp &= ~EMIFS_FCLKDIV_nCS3_MSK;
  tmp |= FCLKDIV;

  /* Commit the Register Update */
  *(UWORD32*)EMIFS_nCS3_CONFIG_REG = tmp;
}